Internal Memory

Internal Memory Core Memory each core held one bit core external diameter: 1/8, 1/16, 1/32 inch Semiconductor Memory  memory cell Control Signal Read/Write Select (activate cell) Memory Cell Semiconductor Memory Cell Properties  two stable (semi-stable) states  capable of being written at least once  capable of being read to sense the state Sense Data Flow Out Data Flow In Data Flow consists of a single bit, i.e., zero or one  RAM Memory o wired-in addressing logic – are used to access individual words o rapid reading & writing is possible o volatile – constant power supply required o temporary storage  ROM/PROM Memory – (read only, programmable read-only) o read-only o non-volatile o permanent storage  EPROM Memory (erasable & programmable) o mostly read-only o erasable & writable via UV light source (off-line) o non-volatile o permanent storage  EEPROM Memory (electronically erasable & programmable) o mostly read-only o electronically erasable & writable (on-line) o non-volatile o permanent storage  Flash Drive Memory o block-level read & write – slow (storage device) o mixed features of both main memory & disk storage o electronically erasable & writable (on-line) o non-volatile o permanent storage RAM Memory -- used for Main Memory DRAM – dynamic RAM  DRAM cells store a charge on a capacitor o presence of a charge indicates 1 o absence of a charge indicates 0  capacitors have a natural tendency to discharge  require periodic recharging  tendency of the stored charge to leak away  dynamic  analog device, i.e., Sense Amplifier measures the Storage Capacitors contents DRAM Address Line Input Value transistor holds one bit Bit Line B Sense Amplifier with a Reference Value Storage Capacitor Ground Transistor acts as a switch  if address line is charged it allows current to flow between the capacitor and bit line B  if address line is not charged it blocks the flow of current between the capacitor and the bit line B Output Value Write Operation 1. Voltage signal is applied to the bit line  High voltage == 1  Low voltage == 0 2. Signal is applied to the address line allowing the charge to be transferred to the capacitor DRAM cells are ANALOG DEVICES since they use a capacitor to hold a voltage charge which must be MEASURED to determine whether it represents a zero or a one, i.e., the capacitor may hold any charge value within a specified range Read Operation 1. Signal is applied to the address line allowing the charge on the capacitor to be released via the bit line to a sense amplifier 2. Sense amplifier compares the capacitor voltage to a reference value and determines whether the cell contains a zero (0) or a one (1) 3. Since the capacitor is now discharged, it must be rewritten to complete the operation SRAM – static RAM – used for Cache Memory  digital device  flip-flop logic-gate  holds data as long as power supply exists  no refresh is required to hold data dc voltage T3 transistor T4 transistor C1 C2 T5 transistor T6 transistor T2 transistor T1 transistor Ground Bit Line B Bit Line B--Address Line Logic State 1 point C1 – high point C2 – low T1 & T4 off T2 & T3 on Logic State 0 point C1 – low point C2 – high T1 & T4 on T2 & T3 off SRAM address line is used to open/close the transistor switches T5 & T6 which allows a read/write operation Write Operation  desired bit value is supplied to bit line B and the complement value is supplied to bit line B--- the four transistors T1, T2, T3, T4 are forced into proper state to hold the desired bit value Read Operation  bit value is read from bit line B DRAM versus SRAM  DRAM cells – main memory o are simpler & smaller than SRAM cells o can be more can be tightly packed together than SRAM cells o inexpensive o require refresh circuitry  SRAM -- cache memory o faster than DRAM – do not require rewriting upon reading ROM Memory        data is permanently in main memory, i.e., read-only program permanently in main memory nonvolatile no power source required information is “burned”, i.e., “hard-wired” into chip during fabrication chip creation must be exact – an error in a single bit invalidates the entire chip run high-volume production runs Usage:     microprogramming library subroutines system programs function tables PROM Memory – programmable ROM      data is permanently in main memory, i.e., read-only after write-once program permanently in main memory nonvolatile no power source required information is electronically inserted into the chip after fabrication using special equipment while the chip is off-line  low or medium volume production runs Write-Mostly Memory   EPROM – erasable programmable ROM o optical media o all storage cells on the chip are erased to an initial state by exposure to an intense ultra-violet light o erasure may be done repeatedly o erasure may take 10-20 minutes to perform o o one transistor per cell more expensive than PROM EEPROM – electronically erasable programmable ROM o rewritable at the byte level without prior erasure o o o o o o  writable in place, i.e., on-line, using ordinary bus control, address & data lines field-effect transistors write operation takes several hundred microseconds per byte, i.e., ≈ 0.5 – 0.01 milliseconds completion time: read operation ≪ write operation more expensive than EPROM less dense than EPROM Flash Memory o rewritable at the block level without prior erasure o one transistor per cell Flash memory is not byte addressable o entire blocks of memory cells are erased in a single flash o erasure of entire flash memory can be accomplished in a few seconds Chip Organization & Functional Logic  Organizational Principle -- number of bits of data read/written at a time o Physical arrangement of cells in the array is the same as the logical arrangement of words in memory, i.e., array contains W words of B bits each, e.g., 16-Mbit chip organized as 1M of 16 bit words o One bit per chip arrangement, data is written 1 bit at a time Row Address Select Column Address Select ____ RAS Page 165, Fig 5.3 4 bits are read/written at a time A0 M U X Row Address Buffer A1 ⋮ Column Address Buffer A10      11 lines ____ WE Output Enable ____ OE 4 data bits transferred, i.e., one per each array Timing & Control Four Arrays 2048 x 2048 Row Decoder Refresh Counter ____ CAS Write Enable 2048 lines ⋮ Memory Array 2048 x 2048 x 4 … # Output Lines = 2 # Input lines 2048 lines D1 Refresh Circuitry Data Input Buffer Column Decoder Data Output Buffer 4 bits are read or written at a time row line connects to the Select terminal of each cell in the row column line connects to the Data-In/Sense terminal of each cell in the column eleven address lines, e.g., A0, A1, …, A10 supply the address of the data item selected 11 decoder activates a single output line depending on the 11 input lines (2 == 2048)  Using DRAM 2048 x 2048 x 4 Memory Array architecture  multiple DRAMs must be connected to a memory controller in order to hold a word of data, e.g., two DRAMs are required to transfer one byte of data  A0, A1, …, A10 are used to pass both row & column address information i. A0, A1, …, A10 are used to pass row address information with the Row Address Select line as well as either the Write Enable line or the Output Enable line set ii. A0, A1, …, A10 are used to pass column address information with the Column Address Select line as well as either the Write Enable line or the Output Enable line set  Using one more address line, e.g., A0, A1, …, A10, A11 doubles the number of rows and 12 columns thus quadrupling the amount of memory on an array, i.e., output rows 2 == 12 4096 and output columns 2 == 4096 yields an array 4096 x 4096 x 4 Note: 4096 x 4096 x 4  67,108,864 whereas 2048 x 2048 x 4  16,777,216 16,777,216 x 4  67,108,864  Refresh Circuitry i. disable DRAM chip ii. the refresh counter selects the row values one at a time; the selected values are supplied to the row decoder and the Row Address Select line is activated. The data is read out and rewritten into the same location thus each cell in the row is refreshed. D2 D3 D4  Chip Packaging o EPROM chip pg 166 fig 5.4 o DRAM chip pg 167 fig 5.5 8 Mbit chip 16 Mbit chip organized as 1M x 8 one word/chip package organized as 4M x 4 4 arrays 2048 x 2048 11 11 22 2 x 2  2  4M NC pin (“no connect” provided to provide even number of pins) Module Organization  RAM chip contains 1 bit per word  n RAM chips required for n bit word, e.g., 8 RAM chips required for byte addressable memory  other configurations become more complex  interleaved memory o main memory composed of a collection of DRAM chips o chips are grouped into memory banks o each bank may independently service a memory request; i.e., o system composed of K banks can simultaneously service K requests o consecutive words stored in different banks  transfer times for memory blocks will be increased Error Correction  Hard Failure – permanent physical defect in the cell  Soft Failure – random, nondestructive event, alters content without damaging the cell o power supply fluctuations o alpha particles – radioactive decay  procedure error correction code function data F(data)  code data + code memory data + code error correction code function data comparison function No Errors detected Error detected; error is correctable destination hardware data Hamming Code code error corrector Error detected but is not correctable SDRAM (Synchronous DRAM)  SDRAM moves data under the control of the system clock, i.e., synchronous access DRAM operation  CPU sends addresses & control information to DRAM  During access time delay, DRAM activates the high capacitance of the row & column lines, senses the data and routes the data to output buffers  CPU must wait during the access time delay see page 175 figure 5.12 for internal logic diagram see page 176 figure 5.13 for timing chart activity  Processor, or surrogate, issues instructions and address information which is latched by the SDRAM  SDRAM responds after a specified number of clock cycles   CPU can engage in other tasks while the SDRAM responds to the request SDRAM provides a mechanism to enable customization of chip operation to meet specific needs of system builders SDRAM performs best when transferring large blocks of data, e.g., multimedia, spreadsheets, word processing  DDR-SDRAM (Double Data Rate SDRAM)  Sends data to the processor twice per clock cycle – one on the leading edge, another on the following edge DDR2-SDRAM DDR3-SDRAM RDRAM (Rambus DRAM)  special RDRAM bus asynchronous block-oriented protocol Intel o defines impedances, clocking, signals very precisely Pentium & Itanium processors o receives memory requests over a high-speed bus o request contains address, type of operation (read/write) and number of bytes desired   RDRAM bus connects to the controller at on end and is terminated at the other end Clock signal originates at the terminated end, propagates to the controller end and is then reflected back to the terminated end  bits are sent at both the leading and the following edge of each clock signal going toward the controller standard usage is send bits only at o signal rate 800 Mbps (cycling twice the clock rate) one of the edges of a clock signal   RDRAM module sends data to the controller synchronously to the master on the forward direction Controller send data to the RDRAM synchronously with the clock signal in the opposite direction  initial 480 nanosec access time, it produces a 1.6 GBps data rate CD-DRAM Integration of a small SRAM cache (16 Bb) onto a generic DRAM chip  used as cache memory  used as a buffer to support serial access of a block of data