University:
California State University, Northridge
Course:
COMP 182 | Data Structures and Program Design and Lab
Academic year:

2023
Views:

69

Pages:

8
Author:

NyiH

Quiz 6 - Interrupts, PSW, Registers, ClocksDue Mar 13 at 11:59pmPoints 15Questions 15Available Mar 7 at 12am - Mar 13 at 11:59pmTime Limit NoneAttempt HistoryAttemptTimeScoreLATESTAttempt 15,597 minutes15 out of 15!Correct answers will be available on Mar 14 at 12:01am.Score for this quiz: 15 out of 15Submitted Mar 11 at 2:10pmThis attempt took 5,597 minutes.Question 11/1 ptsInterrupts have all these properties, except:PriorityPreemptionA sub-class of ExceptionCause no pipeline flush Question 21/1 ptsLow priority devices should use what class of Interrupt:MaskableNMINon-VectoredVectoredQuestion 31/1 ptsWhat is an Interrupt Vector:A byte used by an ISR to decode the identity of an interruptingdeviceAll of theseA byte that can be used by an ISR as a branch target offsetA byte provided by an interrupting device to identify itself Question 41/1 ptsInterrupts are processed if what conditions are met:Pending and maskableVectored with vector present on data busMask and global enable bits are set, it is pending and highestpriorityEnabled and pre-emptiveQuestion 51/1 ptsPSW contains:Process SoftwarePriority Sequence WordProgram SoftwareProgram Status Word Question 61/1 ptsMIPS PSW contains:All of theseStatus registerFlagsInterrupt enablesQuestion 71/1 ptsMIPS CPO contains a Cause register, which contains:Endianness controlInterrupt enablesException code onlyException code + interrupts pending Question 81/1 ptsMIPS CPO contains which registers:BadVAddr + ConfigEPC + CountCause + Statusall of theseQuestion 91/1 ptsRegisters are composed of a linear array of what logic element:NAND gatesD flip-flopsALURS latches Question 101/ 1 ptsWhich sequential logic element is clock-edge triggered:Flip-flopsALULatchesNAND gatesQuestion 111/ 1 ptsWhich clocking scheme helps keep a digital system tightlysynchronized (even used in the i8080):Single-phase clockingRising-edge clockingFalling-edge clocking2-phase clocking Question 121/1 ptsWhat type of logic block is necessary for an FSM - Finite StateMachine:ORegistersLatchesALUDecodersQuestion 131/1 ptsWhat type of analog circuit is necessary for providing a stableclock:PLL, including a VCXOD flip-flopsALUInductors Question 141/1 ptsWhat is used to distribute a system clock to all of the system:PLL treeQuartz crystalRegistersControl busQuestion 151/1 ptsSystem clock stability and skew both impact:Timing marginsPLL'sClock treesDC specs