University:
California State University, Northridge
Course:
COMP 182 | Data Structures and Program Design and Lab
Academic year:

2023
Views:

28

Pages:

8
Author:

NyiH

Question 1 Multi-level memory hierarchy from fastest to slowest: Main 12 cache Registers L1 cache L2 cache Question 2 L1 cache is refilled directly, first from L3 cache Any of these Main memory L2 cache Question 3 RISC CPU'S L1 cache architecture is: Shared cache United rates fre Any these Separate and D caches (Harvard) Question 4 RISC CPU's L2 cache architecture is: Unified caches (von Neumann) Separate land castes Hansend Shared cache Asthete Question 5 RISC CPU's L3 cache architecture is: Unified sachen Seon bleumanni Separate Land D caches (Hananti Any of there Shared unified cache Question 6 Each level of cache memory is approx. N times larger/smaller and faster/slower where N 10 52 Question 7 Cache memory is made from what type of memory: DRAM SRAM ROM EEPROM Question 8 Cache memory in most RISC CPU's now use what type of mapping: set associative drmst fut associate Question 9 Cache is refilled in one chunk at a time, called a block woof Question 10 D-Cache misses in RISC can only be caused by which type of instruction Load or Store Jump Question 11 D-Cache organization that has the simplest hardware implementation. Direct-mapped, Write-through Direct-mapped, Writeck Fily amocatte WWime-back Set mnociative. Witte tha Question 12 I-Cache misses in RISC are most likely to be caused by which type of instruction Jump tuit or Story Branch Question 13 Virtual memory is most likely to be needed in which class of computer system: Desktop computer or Server Embedded Gaming Question 14 Virtual mernory is used by an OS to do this Заттайу гос Any of these Statically locate colle Question 15 Virtual memory uses a Page Table with an on-chip cache called ac SIMU D-cache TLE Direct Page Tale