University:
California State University, Northridge
Course:
COMP 222 | Computer Organization
Academic year:

2016
Views:

398

Pages:

19
Author:

Ivy Werner

+ Computer Organization and Architecture + Chapter 4 Cache Memory Part 1 Location Internal (e.g. processor registers, cache, main memory) External (e.g. optical disks, magnetic disks, tapes) Capacity Number of words Number of bytes Unit of Transfer Word Block Access Method Sequential Direct Random Associative Performance Access time Cycle time Transfer rate Physical Type Semiconductor Magnetic Optical Magneto-optical Physical Characteristics Volatile/nonvolatile Erasable/nonerasable Organization Memory modules Table 4.1 Key Characteristics of Computer Memory Systems + Characteristics of Memory Systems Location Refers to whether memory is internal and external to the computer Internal memory is often equated with main memory Processor requires its own local memory, in the form of registers Cache is another form of internal memory External memory consists of peripheral storage devices that are accessible to the processor via I/O controllers Capacity Memory is typically expressed in terms of bytes Unit of transfer For internal memory the unit of transfer is equal to the number of electrical lines into and out of the memory module Method of Accessing Units of Data Sequential access Direct access Random access Associative Memory is organized into units of data called records Involves a shared readwrite mechanism Each addressable location in memory has a unique, physically wiredin addressing mechanism A word is retrieved based on a portion of its contents rather than its address Access must be made in a specific linear sequence Individual blocks or records have a unique address based on physical location The time to access a given location is independent of the sequence of prior accesses and is constant Each location has its own addressing mechanism and retrieval time is constant independent of location or prior access patterns Access time is variable Any location can be selected at random and directly addressed and accessed Cache memories may employ associative access Access time is variable Main memory and some cache systems are random access Capacity and Performance: The two most important characteristics of memory Three performance parameters are used: Access time (latency) •For random-access memory it is the time it takes to perform a read or write operation •For non-random-access memory it is the time it takes to position the read-write mechanism at the desired location Memory cycle time •Access time plus any additional time required before second access can commence •Additional time may be required for transients to die out on signal lines or to regenerate data if they are read destructively •Concerned with the system bus, not the processor Transfer rate •The rate at which data can be transferred into or out of a memory unit •For random-access memory it is equal to 1/(cycle time) + Memory The most common forms are: Semiconductor memory Magnetic surface memory Optical Magneto-optical Several physical characteristics of data storage are important: Volatile memory Information decays naturally or is lost when electrical power is switched off Nonvolatile memory Once recorded, information remains without deterioration until deliberately changed No electrical power is needed to retain information Magnetic-surface memories Are nonvolatile Semiconductor memory May be either volatile or nonvolatile Nonerasable memory Cannot be altered, except by destroying the storage unit Semiconductor memory of this type is known as read-only memory (ROM) For random-access memory the organization is a key design issue Organization refers to the physical arrangement of bits to form words + Memory Hierarchy Design constraints on a computer’s memory can be summed up by three questions: How much, how fast, how expensive There is a trade-off among capacity, access time, and cost Faster access time, greater cost per bit Greater capacity, smaller cost per bit Greater capacity, slower access time The way out of the memory dilemma is not to rely on a single memory component or technology, but to employ a memory hierarchy gRe r s e i st In b me oard mo ry Ou t sto boar rag d e Of f sto -line rag e ch Ca e in Ma ory m me isk cd i t e gn OM M a D- R W C D- R W R C M DDV D- R A y a DV lu-R B ct et i n g Ma e ap Figure 4.1 The Memory Hierarchy T1 + T2 Average access time T2 T1 0 1 Fraction of accesses involving only Level 1 (Hit ratio) Figure 4.2 Performance of a Simple Two-Level Memory + Memory The use of three levels exploits the fact that semiconductor memory comes in a variety of types which differ in speed and cost Data are stored more permanently on external mass storage devices External, nonvolatile memory is also referred to as secondary memory or auxiliary memory Disk cache A portion of main memory can be used as a buffer to hold data temporarily that is to be read out to disk A few large transfers of data can be used instead of many small transfers of data Data can be retrieved rapidly from the software cache rather than slowly from the disk Block Transfer Word Transfer Main Memory Cache CPU Fast Slow (a) Single cache Level 2 (L2) cache Level 1 (L1) cache CPU Fastest Fast Level 3 (L3) cache Less fast (b) Three-level cache organization Figure 4.3 Cache and Main Memory Main Memory Slow Line Number Tag 0 1 2 Block Memory address 0 1 2 3 Block 0 (K words) C–1 Block Length (K Words) (a) Cache Block M – 1 2n – 1 Word Length (b) Main memory Figure 4.4 Cache/Main-Memory Structure START Receive address RA from CPU Is block containing RA in cache? Access main memory for block containing RA No Yes Allocate cache line for main memory block Fetch RA word and deliver to CPU Load main memory block into cache line Deliver RA word to CPU DONE Figure 4.5 Cache Read Operation Address Processor Control Cache Control Data buffer Data Figure 4.6 Typical Cache Organization System Bus Address buffer Cache Addresses Logical Physical Cache Size Mapping Function Direct Associative Set Associative Replacement Algorithm Least recently used (LRU) First in first out (FIFO) Least frequently used (LFU) Random Write Policy Write through Write back Line Size Number of caches Single or two level Unified or split Table 4.2 Elements of Cache Design + Cache Addresses Virtual Memory Virtual memory Facility that allows programs to address memory from a logical point of view, without regard to the amount of main memory physically available When used, the address fields of machine instructions contain virtual addresses For reads to and writes from main memory, a hardware memory management unit (MMU) translates each virtual address into a physical address in main memory Logical address MMU Physical address Processor Main memory Cache Data (a) Logical Cache Logical address MMU Physical address Processor Cache Data (b) Physical Cache Figure 4.7 Logical and Physical Caches Main memory Year of Introduction 1968 1975 1978 1978 1985 1989 1993 1993 1996 1999 1999 2000 L1 Cachea L2 cache L3 Cache 16 to 32 kB 1 kB 16 kB 64 kB 128 to 256 kB 8 kB 8 kB/8 kB 32 kB 32 kB/32 kB 32 kB/32 kB 256 kB 8 kB/8 kB — — — — — — 256 to 512 KB — — 256 KB to 1 MB 8 MB 256 KB — — — — — — — — — 2 MB — — 2000 64 kB/32 kB 8 MB — 2000 2001 2002 8 kB 16 kB/16 kB 32 kB 2 MB 96 KB 256 KB — 4 MB 6 MB 2003 64 kB 1.9 MB 36 MB 2004 64 kB/64 kB 1MB — PC/server 2007 64 kB/64 kB 4 MB 32 MB Mainframe Workstaton/ server 2008 64 kB/128 kB 3 MB 24-48 MB 2011 6 × 32 kB/32 kB 1.5 MB 12 MB 2011 24 × 64 kB/ 128 kB 24 × 1.5 MB 24 MB L3 192 MB L4 Processor Type IBM 360/85 PDP-11/70 VAX 11/780 IBM 3033 IBM 3090 Intel 80486 Pentium PowerPC 601 PowerPC 620 PowerPC G4 IBM S/390 G6 Pentium 4 Mainframe Minicomputer Minicomputer Mainframe Mainframe PC PC PC PC PC/server Mainframe PC/server High-end server/ supercomputer Supercomputer PC/server PC/server High-end server Supercomputer IBM SP CRAY MTAb Itanium Itanium 2 IBM POWER5 CRAY XD-1 IBM POWER6 IBM z10 Intel Core i7 EE 990 IBM zEnterprise 196 Table 4.3 Cache Sizes of Some Processors a Mainframe/ Server Two values separated by a slash refer to instruction and data caches. b Both caches are instruction only; no data caches. (Table can be found on page 134 in the textbook.)

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