Computer System Architecture

Micro-operations and Control Signals Micro-operations t1: MAR ← (PC) t2: MBR ← Memory Fetch: PC ← (PC) + 1 Indirect: Interrupt: = = C2 C5, CR t3: IR ← (MBR) C4 t1: MAR ← (IR(Address)) C8 t2: MBR ← Memory C5, CR t3: IR(Address) ← (MBR(Address)) C4 t1: MBR ← (PC) C1 t2: MAR ← Save-address PC ← Routine-address t3: Memory ← (MBR) CR CW Active Control Signals Read control signal to system bus. Write control signal to system bus. C12, CW Intel 8085 External Signals Address and Data Signals High Address (A15–A8) The high-order 8 bits of a 16-bit address. Address/Data (AD7 –AD0) The lower-order 8 bits of a 16-bit address or 8 bits of data. This multiplexing saves on pins. Serial Input Data (SID) A single-bit input to accommodate devices that transmit serially (one bit at a time). Serial Output Data (SOD) A single-bit output to accommodate devices that receive serially. Timing and Control Signals CLK (OUT) The system clock. The CLK signal goes to peripheral chips and synchronizes their timing. X1, X2 These signals come from an external crystal or other device to drive the internal clock generator. Address Latch Enabled (ALE) Occurs during the first clock state of a machine cycle and causes peripheral chips to store the address lines. This allows the address module (e.g., memory, I/O) to recognize that it is being addressed. Status (S0, S1) Control signals used to indicate whether a read or write operation is taking place. IO/M Used to enable either I/O or memory modules for read and write operations. Read Control (RD) Indicates that the selected memory or I/O module is to be read and that the data bus is available for data transfer. Write Control (WR) Indicates that data on the data bus is to be written into the selected memory or I/O location. Intel 8085 External Signals Memory and I/O Initiated Symbols Hold Requests the CPU to relinquish control and use of the external system bus. The CPU will complete execution of the instruction presently in the IR and then enter a hold state, during which no signals are inserted by the CPU to the control, address, or data buses. During the hold state, the bus may be used for DMA operations. Hold Acknowledge (HOLDA) This control unit output signal acknowledges the HOLD signal and indicates that the bus is now available. READY Used to synchronize the CPU with slower memory or I/O devices. When an addressed device asserts READY, the CPU may proceed with an input (DBIN) or output (WR) operation. Otherwise, the CPU enters a wait state until the device is ready. Interrupt-Related Signals TRAP Restart Interrupts (RST 7.5, 6.5, 5.5) Interrupt Request (INTR) These five lines are used by an external device to interrupt the CPU. The CPU will not honor the request if it is in the hold state or if the interrupt is disabled. An interrupt is honored only at the completion of an instruction. The interrupts are in descending order of priority. Interrupt Acknowledge Acknowledges an interrupt. CPU Initialization RESET IN Causes the contents of the PC to be set to zero. The CPU resumes execution at location zero. RESET OUT Acknowledges that the CPU has been reset. The signal can be used to reset the rest of the system. Voltage and Ground VCC +5-volt power supply VSS Electrical ground