Computer Memory Systems

Table 4.1 Key Characteristics of Computer Memory Systems Location Internal (e.g. processor registers, main memory, cache) External (e.g. optical disks, magnetic disks, tapes) Capacity Number of words Number of bytes Unit of Transfer Word Block Access Method Sequential Direct Random Associative Performance Access time Cycle time Transfer rate Physical Type Semiconductor Magnetic Optical Magneto-optical Physical Characteristics Volatile/nonvolatile Erasable/nonerasable Organization Memory modules Table 4.2 Elements of Cache Design Cache Addresses Logical Physical Cache Size Mapping Function Direct Associative Set Associative Replacement Algorithm Least recently used (LRU) First in first out (FIFO) Least frequently used (LFU) Random Write Policy Write through Write back Write once Line Size Number of caches Single or two level Unified or split Table 4.3 Year of Introduction 1968 1975 1978 1978 1985 1989 1993 1993 1996 1999 1997 1999 2000 L1 Cachea L2 cache L3 Cache 16 to 32 kB 1 kB 16 kB 64 kB 128 to 256 kB 8 kB 8 kB/8 kB 32 kB 32 kB/32 kB 32 kB/32 kB 32 kB 256 kB 8 kB/8 kB — — — — — — 256 to 512 KB — — 256 KB to 1 MB 256 KB 8 MB 256 KB — — — — — — — — — 2 MB 2 MB — — 2000 64 kB/32 kB 8 MB — 2000 2001 8 kB 16 kB/16 kB 2 MB 96 KB — 4 MB 2001 32 kB/32 kB 4 MB — 2002 32 kB 256 KB 6 MB 2003 64 kB 1.9 MB 36 MB 2004 64 kB/64 kB 1MB — PC/server 2007 64 kB/64 kB 4 MB 32 MB Mainframe 2008 64 kB/128 kB 3 MB 24-48 MB Processor Type IBM 360/85 PDP-11/70 VAX 11/780 IBM 3033 IBM 3090 Intel 80486 Pentium PowerPC 601 PowerPC 620 PowerPC G4 IBM S/390 G4 IBM S/390 G6 Pentium 4 Mainframe Minicomputer Minicomputer Mainframe Mainframe PC PC PC PC PC/server Mainframe Mainframe PC/server High-end server/ supercomputer Supercomputer PC/server High-end server PC/server High-end server Supercomputer IBM SP CRAY MTAb Itanium SGI Origin 2001 Itanium 2 IBM POWER5 CRAY XD-1 IBM POWER6 IBM z10 a b Cache Sizes of Some Processors Two values separated by a slash refer to instruction and data caches. Both caches are instruction only; no data caches. Table 4.4 Problem Intel Cache Evolution Solution Add external cache using External memory slower than the system faster memory bus. technology. Move external cache onIncreased processor speed results in chip, operating at the external bus becoming a bottleneck for same speed as the cache access. processor. Add external L2 cache Internal cache is rather small, due to using faster technology limited space on chip than main memory Contention occurs when both the Create separate data and Instruction Prefetcher and the Execution instruction caches. Unit simultaneously require access to the cache. In that case, the Prefetcher is stalled while the Execution Unit’s data access takes place. Create separate back-side bus that runs at higher speed than the main Increased processor speed results in (front-side) external bus. external bus becoming a bottleneck for L2 The BSB is dedicated to cache access. the L2 cache. Move L2 cache on to the processor chip. Some applications deal with massive Add external L3 cache. databases and must have rapid access to large amounts of data. The on-chip caches Move L3 cache on-chip. are too small. Processor on which Feature First Appears 386 486 486 Pentium Pentium Pro Pentium II Pentium III Pentium 4 Table 4.5 Pentium 4 Cache Operating Modes Control Bits Operating Mode CD NW Cache Fills Write Throughs Invalidates 0 0 Enabled Enabled Enabled 1 0 Disabled Enabled Enabled 1 1 Disabled Disabled Disabled Note: CD = 0; NW = 1 is an invalid combination. Table 4.6 ARM Cache Features Core Cache Type Cache Size (kB) Cache Line Size (words) Associativity Location Write Buffer Size (words) ARM720T Unified 8 4 4-way Logical 8 ARM920T Split 16/16 D/I 8 64-way Logical 16 ARM926EJ-S Split 4-128/4128 D/I 8 4-way Logical 16 ARM1022E Split 16/16 D/I 8 64-way Logical 16 ARM1026EJ-S Split 4-128/4128 D/I 8 4-way Logical 8 Intel StrongARM Split 16/16 D/I 4 32-way Logical 32 Intel Xscale Split 32/32 D/I 8 32-way Logical 32 ARM1136-JF-S Split 4-64/4-64 D/I 8 4-way Physical 32 Table 4.7 Characteristics of Two-Level Memories Main Memory Cache Virtual Memory (paging) Disk Cache Typical access time ratios 5 : 1 (main memory vs. cache) 106 : 1 (main memory vs. disk) 106 : 1(main memory vs. disk) Memory management system Implemented by special hardware Combination of hardware and system software System software Typical block or page size size 4 to 128 bytes (cache block) 64 to 4096 bytes 64 to 4096 bytes (disk (virtual memory page) block or page)s Access of processor to second level Direct access Indirect access Indirect access Table 4.8 Relative Dynamic Frequency of High-Level Language Operations Study [HUCK83] [KNUT71] [PATT82a] [TANE78] Language Pascal FORTRAN Pascal C SAL Workload Scientific Student System System System Assign 74 67 45 38 42 Loop 4 3 5 3 4 Call 1 3 15 12 12 IF 20 11 29 43 36 GOTO 2 9 — 3 — Other — 7 6 1 6