University:
California State University, Northridge
Course:
ECE 496A-Z | Experimental Topics Courses in Electrical and Computer Engineering
Academic year:

2006
Views:

176

Pages:

54
Author:

thitinnlc0

TMS320C6000 Architectural Overview Learning Objectives     Describe C6000 CPU architecture. Introduce some basic instructions. Describe the C6000 memory map. Provide an overview of the peripherals. General DSP System Block Diagram Internal Memory Internal Buses External Memory Central Processing Unit P E R I P H E R A L S What are the typical DSP algorithms?  The Sum of Products (SOP) is the key element in most DSP algorithms: Algorithm Finite Impulse Response Filter Equation y ( n) = M ∑a k x(n − k ) k =0 Infinite Impulse Response Filter y ( n) = M ∑a k k =0 Convolution y ( n) = x ( n − k )+ N ∑b k y (n − k ) k =1 N ∑ x ( k ) h( n − k ) k =0 Discrete Fourier Transform X (k ) = N −1 ∑ x(n) exp[− j(2π / N )nk ] n =0 Discrete Cosine Transform F (u ) = N −1  π  ∑ c(u). f ( x). cos 2 N u(2 x + 1) x =0 Implementation of Sum of Products (SOP) It has been shown that SOP is the key element for most DSP algorithms. So let’s write the code for this algorithm and at the same time discover the C6000 architecture. N Y = ∑ n = 1 an * xn = a1 * x1 + a2 * x2 +... + aN * xN Two basic operations are required for this algorithm. (1) Multiplication (2) Addition Therefore two basic instructions are required Implementation of Sum of Products (SOP) So let’s implement the SOP algorithm! N Y = ∑ n = 1 an * xn = a1 * x1 + a2 * x2 +... + aN * xN The implementation in this module will be done in assembly. Two basic operations are required for this algorithm. (1) Multiplication (2) Addition Therefore two basic instructions are required Multiply (MPY) N Y = ∑ n = 1 an * xn = a1 * x1 + a2 * x2 +... + aN * xN The multiplication of a1 by x1 is done in assembly by the following instruction: MPY a1, x1, Y This instruction is performed by a multiplier unit that is called “.M” Multiply (.M unit) 40 Y = ∑ n = 1 .M an * xn The . M unit performs multiplications in hardware MPY .M a1, x1, Y Note: 16-bit by 16-bit multiplier provides a 32-bit result. 32-bit by 32-bit multiplier provides a 64-bit result. Addition (.?) 40 Y = ∑ n = 1 an * xn .M .? MPY .M a1, x1, prod ADD .? Y, prod, Y Add (.L unit) 40 Y = ∑ n = 1 an * xn .M .L MPY .M a1, x1, prod ADD .L Y, prod, Y RISC processors such as the C6000 use registers to hold the operands, so lets change this code. Register File - A A0 A1 A2 A3 40 Register File A Y = ∑ a1 x1 n = 1 prod Y .M . . . .L an * xn MPY .M a1, x1, prod ADD .L Y, prod, Y A15 32-bits Let us correct this by replacing a, x, prod and Y by the registers as shown above. Specifying Register Names A0 A1 A2 A3 40 Register File A Y = ∑ a1 x1 n = 1 prod Y .M . . . .L an * xn MPY .M A0, A1, A3 ADD .L A4, A3, A4 A15 32-bits The registers A0, A1, A3 and A4 contain the values to be used by the instructions. Specifying Register Names A0 A1 A2 A3 40 Register File A Y = ∑ a1 x1 n = 1 prod Y .M . . . .L an * xn MPY .M A0, A1, A3 ADD .L A4, A3, A4 A15 32-bits Register File A contains 16 registers (A0 -A15) which are 32-bits wide. Data loading A0 A1 A2 A3 Register File A Q: How do we load the operands into the registers? a1 x1 prod Y .M . . . .L A15 32-bits Load Unit “.D” A0 A1 A2 A3 Register File A Q: How do we load the operands into the registers? a1 x1 prod Y .M . . . .L .D A15 32-bits Data Memory A: The operands are loaded into the registers by loading them from the memory using the .D unit. Load Unit “.D” A0 A1 A2 A3 Register File A a1 x1 prod Y .M . . . .L .D A15 32-bits Data Memory It is worth noting at this stage that the only way to access memory is through the .D unit. Load Instruction A0 A1 A2 A3 Register File A a1 x1 prod Y .M . . . .L .D A15 32-bits Data Memory Q: Which instruction(s) can be used for loading operands from the memory to the registers? Load Instructions (LDB, LDH,LDW,LDDW) A0 A1 A2 A3 Register File A a1 x1 prod Y .M . . . .L .D A15 32-bits Data Memory Q: Which instruction(s) can be used for loading operands from the memory to the registers? A: The load instructions. Using the Load Instructions Before using the load unit you have to be aware that this processor is byte addressable, which means that each byte is represented by a unique address. Data address 00000000 00000002 00000004 00000006 00000008 Also the addresses are 32-bit wide. FFFFFFFF 16-bits Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm Where: Rn is a register that contains the address of the operand to be loaded Data address a1 x1 00000000 00000002 00000004 00000006 00000008 prod Y and Rm is the destination register. FFFFFFFF 16-bits Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm The question now is how many bytes are going to be loaded into the destination register? Data address a1 x1 00000000 00000002 00000004 00000006 00000008 prod Y FFFFFFFF 16-bits Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm The answer, is that it depends on the instruction you choose: Data address a1 x1 00000000 00000002 00000004 00000006 00000008 prod Y • LDB: loads one byte (8-bit) • LDH: loads half word (16-bit) • LDW: loads a word (32-bit) • LDDW: loads a double word (64-bit) Note: LD on its own does not exist. FFFFFFFF 16-bits Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm Example: If we assume that A5 = 0x4 then: (1) LDB *A5, A7 ; gives A7 = 0x00000001 1 Data 0 0xA 0xB 0xC 0xD 0x2 0x1 0x4 0x3 0x6 0x5 0x8 0x7 address 00000000 00000002 00000004 00000006 00000008 (2) LDH *A5,A7; gives A7 = 0x00000201 (3) LDW *A5,A7; gives A7 = 0x04030201 (4) LDDW *A5,A7:A6; gives A7:A6 = 0x0807060504030201 FFFFFFFF 16-bits Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm Question: If data can only be accessed by the load instruction and the .D unit, how can we load the register pointer Rn in the first place? Data address 0xA 0xB 0xC 0xD 0x2 0x1 0x4 0x3 0x6 0x5 0x8 0x7 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits Loading the Pointer Rn  The instruction MVKL will allow a move of a 16-bit constant into a register as shown below: MVKL .? a, A5 (‘a’ is a constant or label)  How many bits represent a full address? 32 bits  So why does the instruction not allow a 32-bit move? All instructions are 32-bit wide (see instruction opcode). Loading the Pointer Rn  To solve this problem another instruction is available: MVKH eg. MVKH .? a, A5 (‘a’ is a constant or label)  ah al a ah x A5 Finally, to move the 32-bit address to a register we can use: MVKL a, A5 MVKH a, A5 Loading the Pointer Rn  Always use MVKL then MVKH, look at the following examples: Example 1 A5 = 0x87654321 MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC (sign extension) MVKH 0x1234FABC, A5 A5 = 0x1234FABC ; OK Example 2 MVKH A5 = 0x12344321 0x1234FABC, A5 MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC ; Wrong LDH, MVKL and MVKH Register File A A0 A1 A2 A3 A4 a x prod Y .M . . . .L .D A15 MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 32-bits pt1 and pt2 point to some locations Data Memory in the data memory. Creating a loop So far we have only implemented the SOP for one tap only, i.e. Y= a1 * x1 So let’s create a loop so that we can implement the SOP for N Taps. MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 Creating a loop So far we have only implemented the SOP for one tap only, i.e. Y= a1 * x1 So let’s create a loop so that we can implement the SOP for N Taps. With the C6000 processors there are no dedicated instructions such as block repeat. The loop is created using the B instruction. What are the steps for creating a loop 1. Create a label to branch to. 2. Add a branch instruction, B. 3. Create a loop counter. 4. Add an instruction to decrement the loop counter. 5. Make the branch conditional based on the value in the loop counter. 1. Create a label to branch to loop MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 2. Add a branch instruction, B. loop MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop Which unit is used by the B instruction? A0 A1 A2 A3 Register File A a x .S prod Y .M .M . . . .L .L .D .D A15 32-bits Data Memory loop MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop Which unit is used by the B instruction? A0 A1 A2 A3 Register File A a x .S prod Y .M .M . . . .L .L .D .D A15 32-bits Data Memory loop MVKL .S MVKH .S pt1, A5 pt1, A5 MVKL .S MVKH .S pt2, A6 pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop 3. Create a loop counter. A0 A1 A2 A3 Register File A a x .S prod Y .M .M . . . .L .L .D .D A15 32-bits Data Memory loop MVKL .S MVKH .S pt1, A5 pt1, A5 MVKL .S MVKH .S MVKL .S pt2, A6 pt2, A6 count, B0 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop B registers will be introduced later 4. Decrement the loop counter A0 A1 A2 A3 Register File A a x .S prod Y .M .M . . . .L .L .D .D A15 32-bits Data Memory loop MVKL .S MVKH .S pt1, A5 pt1, A5 MVKL .S MVKH .S MVKL .S pt2, A6 pt2, A6 count, B0 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop 5. Make the branch conditional based on the value in the loop counter  What is the syntax for making instruction conditional? [condition] Instruction [B1] loop Label e.g. B (1) The condition can be one of the following registers: A1, A2, B0, B1, B2. (2) Any instruction can be conditional. 5. Make the branch conditional based on the value in the loop counter  The condition can be inverted by adding the exclamation symbol “!” as follows: [!condition] Instruction Label [!B0] B loop ;branch if B0 = 0 [B0] B loop ;branch if B0 != 0 e.g. 5. Make the branch conditional A0 A1 A2 A3 MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 Register File A a x .S prod Y .M .M . . . .L .L .D .D A15 32-bits Data Memory MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 loop [B0] LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop More on the Branch Instruction (1)  With this processor all the instructions are encoded in a 32-bit.  Therefore the label must have a dynamic range of less than 32-bit as the instruction B has to be coded. 32-bit B  Case 1: 21-bit relative address B .S1 label  Relative branch.  Label limited to +/- 220 offset. More on the Branch Instruction (2)  By specifying a register as an operand instead of a label, it is possible to have an absolute branch.  This will allow a dynamic range of 232. 32-bit B  Case 2: B .S2  Absolute branch.  Operates on .S2 ONLY! 5-bit register code register Testing the code MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 This code performs the following operations: loop a0*x0 + a0*x0 + a0*x0 + … + a0*x0 However, we would like to perform: a0*x0 + a1*x1 + a2*x2 + … + aN*xN [B0] LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Modifying the pointers MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 The solution is to modify the pointers loop A5 and A6. [B0] LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Indexing Pointers Syntax Description *R Pointer Pointer Modified No In this case the pointers are used but not modified. R can be any register Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] Pointer + Pre-offset - Pre-offset Pointer Modified No No No In this case the pointers are modified BEFORE being used and RESTORED to their previous values.    [disp] specifies the number of elements size in DW (64-bit), W (32-bit), H (16-bit), or B (8-bit). disp = R or 5-bit constant. R can be any register. Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] Pointer + Pre-offset - Pre-offset Pre-increment Pre-decrement Pointer Modified No No No Yes Yes In this case the pointers are modified BEFORE being used and NOT RESTORED to their Previous Values. Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] *R++[disp] *R--[disp] Pointer + Pre-offset - Pre-offset Pre-increment Pre-decrement Post-increment Post-decrement Pointer Modified No No No Yes Yes Yes Yes In this case the pointers are modified AFTER being used and NOT RESTORED to their Previous Values. Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] *R++[disp] *R--[disp] Pointer + Pre-offset - Pre-offset Pre-increment Pre-decrement Post-increment Post-decrement    Pointer Modified No No No Yes Yes Yes Yes [disp] specifies # elements - size in DW, W, H, or B. disp = R or 5-bit constant. R can be any register. Modify and testing the code MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 This code now performs the following operations: loop a0*x0 + a1*x1 + a2*x2 + ... + aN*xN [B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Store the final result MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 This code now performs the following operations: loop a0*x0 + a1*x1 + a2*x2 + ... + aN*xN [B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop STH .D A4, *A7 Store the final result MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 The Pointer A7 has not been initialised. loop [B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop STH .D A4, *A7 Store the final result MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 pt3, A7 MVKH .S2 pt3, A7 MVKL .S2 count, B0 The Pointer A7 is now initialised. loop [B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop STH .D A4, *A7 What is the initial value of A4? MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 A4 is used as an accumulator, so it needs to be reset to zero. loop [B0] MVKL MVKH MVKL ZERO LDH .S2 .S2 .S2 .L .D pt3, A7 pt3, A7 count, B0 A4 *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop STH .D A4, *A7

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