University:
Massachusetts Institute of Technology
Course:
6.012 | Microelectronic Devices and Circuits
Academic year:

2023
Views:

326

Pages:

20
Author:

Henry A

Lecture 20 Transistor Ampliﬁers (II) Other Amplifier Stages November 17, 2005 Contents: 1. Commonsource ampliﬁer (cont.) 2. Commondrain ampliﬁer 3. Commongate ampliﬁer Reading assignment: Howe and Sodini, Ch. 8, §§8.78.9 Key questions • What other ampliﬁer stages can one build with a sin gle MOSFET and a current source? • What is the uniqueness of these other stages? 1. Commonsource ampliﬁer with currentsource supply VDD iSUP signal source iD RS signal� load + vs vOUT VGG - RL VSS Loadline view: load line iSUP=ID VGG-VSS=VDD-VSS ISUP VGG-VSS VGG-VSS=VT 0 VSS VDD VOUT Current source characterized by high output resistance: roc. Then, unloaded voltage gain of commonsource stage: |Avo | = gm (ro //roc ) signiﬁcantly higher than ampliﬁer with resistive supply. Can implement current source supply by means of p channel MOSFET: VDD VB iSUP signal source iD RS + vOUT vs VGG VSS • Relationship between circuit ﬁgures of merit and device parameters Remember: � � � � � � gm = 2 W µnCox ID L 1 L ro � ∝ λnID ID Then: Circuit Parameters Rin Rout Device ∗ |Avo | Parameters gm (ro//roc ) ∞ ro//roc ISU P ↑ ↓ ↓ W ↑ ↑ µnCox ↑ ↑ L↑ ↑ ↑ ∗ adjustments are made to VGG so none of the other parameters change CS amp with current supply source is good voltage am pliﬁer (Rin high and |Av | high), but Rout high too ⇒ voltage gain degraded if RL � ro//roc . Commonsource ampliﬁer is acceptable voltage ampliﬁer (want high Rin, high Avo , low Rout ): RS vs Rout + vin + − − Rin + − Avovin RL ... but excellent transconductance ampliﬁer (want high Rin, high Gmo , high Rout ): iout RS vs + − + vin − Rin For commonsource ampliﬁer: Gmo = gm Gmovin Rout RL + vout − Commonsource ampliﬁer does not work as transresis tance ampliﬁer (want low Rin, high Rmo , low Rout ): iin is RS Rout Rin + − Rmoiin RL nor as current ampliﬁer (want low Rin, high Aio , high Rout ): iin is RS iout Rin Need new ampliﬁer conﬁgurations. Aioiin Rout RL + vout − 2. Commondrain ampliﬁer VDD signal source RS + vs iSUP vOUT signal� load RL VGG VSS How does it work? • VGG, ISU P , and W/L selected to bias MOSFET in saturation, obtain desired output bias point, and de sired output swing. • vG ↑ ⇒ iD can’t change ⇒ vOU T ↑ (source follower) • to ﬁrst order, no voltage gain: vout � vs • but Rout small: eﬀective voltage buﬀer stage (good for making voltage amp in combination with commonsource stage). � Smallsignal analysis Unloaded smallsignal equivalent circuit model: + D G + vgs vin gmvgs - S + roc - + ro vout - + vgs - vin + gmvgs ro//roc - vout - vin = vgs + vout vout = gmvgs(ro //roc) Then: Avo = gm �1 1 gm + ro //roc Input impedance: Rin = ∞ Output impedance: + RS it + vgs - + vin gmvgs ro//roc - - vt vgs=-vt effectively:� resistance of � value 1/gm Rout it + gmvt ro//roc 1 1 = � 1 gm gm + ro //r oc small! Loaded voltage gain: Av = Avo RL RL � 1 � 1 RL + Rout RL + gm - vt � Eﬀect of back bias: If MOSFET not fabricated on isolated pwell, then body is tied up to wafer substrate (connected to VSS ): VDD signal source RS VSS + vs iSUP vOUT signal� load RL VGG VSS Two consequences: • Bias aﬀected: VT depends on VBS = VSS − VOU T = � 0 • Smallsignal ﬁgures of merit aﬀected: signal shows up between B and S (vbs = −vout). Smallsignal equivalent circuit model: + + D G vgs vin gmvgs ro - S - + vbs - gmbvbs roc vout +B - vbs=-vout + + vgs - vin + gmvgs gmbvout - ro//roc vout - gm gm Avo = � <1 1 g + g gm + gmb + ro //r m mb oc Also: Rout = 1 1 gm + gmb + ro //r oc 1 � gm + gmb � Relationship between circuit ﬁgures of merit and device parameters: � � � � � � gm = 2 gmb W µnCox ID L γ = gm 2 −2φp − VBS � Circuit Parameters Device ∗ |Avo | Rin Rout 1 m Parameters gmg+g ∞ gm+gmb mb ISU P ↑ ↓ W ↑ ↓ µnCox ↑ ↓ L↑ ↑ ∗ adjustments are made to VGG so none of the other parameters change CD amp useful as a voltage buﬀer to drive small loads (in a multistage amp, other stages will be used to provide voltage gain). 3. Commongate ampliﬁer Need to handle currentmode signal sources: VDD iSUP iOUT VSS signal� load RL signal source is RS IBIAS VSS How does it work? • since source is signal input terminal, body cannot be tied up to source (Cdb is signiﬁcant) • iSU P , IBIAS , and W/L selected to bias MOSFET in saturation, obtain desired output bias point, and de sired output swing • iS ↑ ⇒ iD ↓ ⇒ iOU T ↓ • no current gain: is = −iout (current buﬀer) � Bias: select ISU P , IBIAS , and W/L to get proper qui escent IOU T and keep MOSFET in saturation. VDD ISUP IOUT VSS IBIAS VSS ISU P + IOU T + IBIAS = 0 Select bias so that IOU T = 0 ⇒ VOU T = 0. Assume MOSFET in saturation (no channel modulation): ID = W µnCox (VGS − VT )2 = ISU P = −IBIAS 2L but VT depends on VBS : � � VT = VT o + γn( −2φp − VBS − −2φp ) Must solve these two equations iteratively to get VS . � Smallsignal circuit (unloaded) iout D + G vgs gmvgs gmbvbs ro - S - roc vbs is + B vbs=vgs - is vgs gmvgs gmbvgs ro gm gmb ro + iout is iout is = −iout ⇒ Aio = − iout = −1 is Not surprising, since in a MOSFET: ig = 0. Input resistance: + vgs gmvgs gmbvgs ro - roc + it vt - vgs=-vt + gmvt it gmbvt ro vt roc//RL - Do KCL on input node: vt − (roc //RL )it it − gmvt − gmbvt − =0 ro Then: L 1 + roc //R 1 ro Rin = � gm + gmb + r1o gm + gmb Very small. RL Output resistance: + vgs gmvgs gmbvgs it ro - + roc - vt RS � + vgs gmvgs gmbvgs it' ro + - - vt' RS Do KCL on input node: i�t vt� + vgs − gmvgs − gmb vgs − =0 ro Notice also: vgs = −i�tRS Then: Rout 1 = roc//{ro [1+RS (gm +gmb + )]} � roc//[ro (1+gm RS )] ro Very large, because of the feedback eﬀect of RS . Summary of MOSFET ampliﬁer stages: stage common source common drain common gate key function Avo , Gmo , Aio Rin Rout Gmo = gm ∞ ro //roc transconductance amp. ∞ 1 gm +gmb voltage buﬀer 1 gm +gmb roc //[ro(1 + gm RS )] current buﬀer Avo � gm gm +gmb Aio � −1 In order to design ampliﬁers with suitable performance, need to combine these stages ⇒ multistage ampliﬁers Key conclusions Diﬀerent MOSFET stages designed to accomplish diﬀer ent goals: • Commonsource stage: – large voltage gain and transconductance, high in put resistance, large output resistance – excellent transconductance ampliﬁer, reasonable volt age ampliﬁer • Commondrain stage: – no voltage gain, but high input resistance and low output resistance – good voltage buﬀer • Commongate stage: – no current gain, but low input resistance and high output resistance – good current buﬀer

Lecture 20 - Transistor Amplifiers (II): Other Amplifier Stages

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