Inverter Analysis and Design

6.012 - Microelectronic Devices and Circuits – Fall 2009 Inverter Analysis and Design The inverter stage is a basic building block for digital logic circuits and memory cells. A generic inverter stage is illustrated below on the left. It consists of two devices, a pull-up device, which is typically either a bipolar junction transistor or an enhancement mode field effect transistor, and a pull-down device, which might be another transistor, or a resistor, current source, diode, etc. The stage load which is shown in the figure represents the input resistance of the following stage, which is typically a stage (or n stages) just like the original stage. + VDD + VDD Pull Up Pull Up + vIN - iSL(vOUT) [ = n iIN(vOUT)] iPD (vIN, vOUT) + + Pull Down iPU(vIN, vOUT) vOUT Stage Load iIN(vIN) + vIN - Pull Down - (a) A generic inverter stage vOUT Stage Load - (b) The static currents to calculate vOUT(vIN) An important piece of information about an inverter stage is its static transfer characteristic, vOUT(vIN). To calculate this characteristic we sum the currents into the output node of the inverter, as is illustrated above on the right. With all of these currents written as functions of vIN and vOUT, this sum yields the desired relationship: iPU(vIN, vOUT) = iPD(vIN, vOUT) + iSL(vOUT) As an example, consider the MOSFET inverter circuit shown at the top of the next page with an n-channel MOSFET pull-down and a resistor pull-up. The MOSFET is characterized by its K-value and by its threshold voltage, VT (we will assume for simplicity that α is 1). To analyze this circuit we not first that with a MOSFET pulldown, the static input current is zero and if the stage output is connected to the input of a similar stage, the static stage load current will also be zero, and the equation above is simply iPU = iPD. With a resistor pull-up, the pull-up current, iPU, is (VDD - vOUT)/R and the pull-down current, iPD, is the MOSFET drain current. This current depends on the gate-to-source voltage, vGS, which is the same as vIN, and the drain-to-source voltage, vDS, which is the same as vOUT. With vIN less than VT, the pull-down current is zero and vOUT is VDD. As vIN increases past VT, vOUT will initially be larger than 1 (vIN - VT), and the device will be in saturation so that iPD will be K(vIN - VT)2/2. vOUT is found by setting iPD equal to iPU: iPU = iPD + VDD iPU = (V - vOUT)/R R iSL = 0 + iPD = 0 if (vIN - VT) < 0 < vOUT = K(vIN - VT)^2/2 if 0 < (vIN - VT) < vOUT = K(vIN - VT - vOUT/2)vOUT if 0 < vOUT < (vIN - VT) iIN = 0 + vIN VT , K - vOUT - A MOSFET inverter with an n-channel MOSFET pull-down and resistor pull-up. Substituting yields (VDD - vOUT)/R = K(vIN - VT)2/2 which we solve for vOUT vOUT = VDD - RK(vIN - VT)2/2 Clearly vOUT decreases as vIN increases. When vOUT reaches vIN - VT, the pull-down goes from saturation to the linear region and iPD changes to K(vIN - VT - vOUT/2)vOUT, and the desired relationship is found by solving the quadratic (VDD - vOUT)/R = K(vIN - VT - vOUT/2)vOUT The resulting transfer characteristic is plotted in the course text in Figure 15.8. Curves for other pull-up devices are also shown in this section of the text. We can identify six features of a given inverter design which we can use to evaluate it and compare it to other designs. They are: 1. 2. 3. 4. 5. 6. The logic levels, VHI, and VLO The noise margins The switching times, τHI→LO, and τLO→HI The power dissipation The fan-out and fan-in sensitivities The manufacturability 2 The logic levels are found by insisting that VHI and VLO are such that VHI applied to the input of an inverter results in an output of VLO, and that VLO applied to the input of an inverter results in an output of VHI. Mathematically, if the transfer characteristic is vOUT = f(vIN), we must find the solutions to the equation vOUT = f(f(vOUT)). For useful inverter stages there will be three solutions to this equation, but only the largest and smallest values are valid; the middle solution is unstable and will not be realized in practice. VHI and VLO are often most easily found with the aid of the graphical technique shown in Figure 15.5 of the course text. To determine the switching times we must first recognize that the reason an inverter output does not instantaneously change in response to an change of its input is because there is charge stored on the output node (on the gate of the load stage, for example, if we are discussing inverters with MOSFET pull-downs as in our earlier example). This is illustrated below: +V Pull Up + + vIN - Pull Down vOUT qN(vOUT) Stage Load - The generic inverter stage with the non-linear charge store shown explicitly. When the input is switched from VHI to VLO, the pull down device typically turns off (so iPD = 0), and the output switches from VLO to VHI. When this happens the output node must be charged up, and this charge is supplied by the pull-up device. This was illustrated on the left in the next figure. The charging current, iCH, which is dqN/dt, is the difference between iPU and iSL (assuming as is usually the case that iPD = 0): iCH ≈ iPU - iSL = dqN/dt The larger this current, the faster the charge store changes, and the faster the output switches. (Note that the corresponding statements can be made about the discharging cycle shown on the right in the figure.) In general the charge stored on the output node, qN, will be a non-linear function of vOUT, and it will not be possible to calculate vOUT(t) and determine the switching time analytically. There are two cases in which we can calculate the switching time, 3 however, and to the extent that we can approximate a given situation as one or the other of these to cases, we can estimate the switching time analytically. The first special case is when the charging (or discharging) current is constant. We can calculate the change in the amount of stored charge when vOUT changes from VLO to VHI, and knowing this the charging time is simply this charge divided by the + VDD Pull Up + VDD iPU(vIN, vOUT) Pull Up iSL(vOUT) [ = n iIN(vOUT)] iIN(vIN) + vIN = VLO - iPD = 0 Pull down off qN(vOUT) iSL(vOUT) [ = n iIN(vOUT)] iPD (vIN, vOUT) iCH + iIN(vIN) vOUT Stage Load VLO ! VHI - (a) Finding τLO→HI (charging cylce) vIN: VHI→VLO; vOUT: VLO →VHI iCH = iPU - iPD - iSL iPU(vIN, vOUT) + vIN = VHI - Pull Down + iDCH vOUT Stage Load qN(vOUT) VHI ! VLO - (b) Finding τHI→LO (discharge cycle) vIN: VLO →VHI; vOUT: VHI→VLO; iDCH = iPD - iPU + iSL charging current, which we have approximated as being constant, ICH (we can say the same about the discharge cycle): τLO→HI ≈ ΔqN/ICH, and τHI→LO ≈ - ΔqN/IDCH [Note: frequently designers do not require that the node be completely charged, but say the node has switched when 90% of the store has been built up (in which case, of course, ΔqN is replaced by 0.9 ΔqN]. The second special case is if the charge store can be modeled as a linear capacitor, CL (i.e., qN ≈ CLvOUT). Then we can write dvOUT/dt = iCH(vOUT)/CL to get a differential equation for vOUT(t). We should be able to solve this equation numerically, if we can not do so analytically. If the charge store can be modeled as a linear capacitor and the charging and dischargind currents can be modeled as constant, then τLO→HI ≈ CL(VHI - VLO)/ICH, and 4 τHI→LO ≈ CL(VHI - VLO)/IDCH We have already included the transient when the input is switched from VLO to VHI in our discussion, but just to make sure this is clear, in this part of the cycle, the pull down device turns on and the output switches from VHI to VLO. The most important difference is that the charge store now discharges and does so through the pull-down device. The pull-down device must conduct this discharge current and the current flowing through the pull-up device (less that into the stage load). In this case, a large pull-up device current is not desirable because it makes this switching time long, whereas a large pull-up current makes the other switching time short. In practice one usually wants to minimize the sum of these two switching times which means that we in general want to design the circuit to have equal magnitude charging and discharging currents, if possible. An example to the switching transient situation in the MOSFET inverter with a resistive pull-up that we illustrated earlier is shown in the figures below. The gate capacitance of the loading stage(s) has been modeled as a linear capacitor. The charging of the store clearly occurs with an RC time constant exponential; the discharging transient is more complex (and typically is much the shorter of the two). +V +V iPU = (V - vOUT)/R iPU = (V - vOUT)/R R R iDCH = iPD - iPU iCH = iPU + + vIN = VLO - OFF vOUT VLO !VHI + i PD CL - (a) Finding τLO→HI (charging cylce) vIN: VHI→VLO; vOUT: VLO →VHI iCH = iPU + vIN = VHI - vOUT VHI !VLO CL VT , K - (b) Finding τHI→LO (discharge cycle) vIN: VLO →VHI; vOUT: VHI→VLO; iDCH = iPD - iPU The power dissipation consists of two components. One is the static power; the other is the dynamic, or switching, power. Then the ouput is high, the static power dissipated is VDDIPU(output high); when the output is low, the static power dissipated is VDDIPU(output low). To get one number to work with we commonly say an average inverter will have its output high half the time, on average, and low the other half. Thus the average static power dissipation is (VDDIPU(output high) + VDDIPU(output low))/2. 5 The dynamic power dissipation is due the fact that each low-high-low cycle the output node is charged to roughly VDD, and then discharged to roughly zero volts. If we can approximate the node charge store with a linear capacitor, CL, the energy dissipated in charging it to VDD is CLVDD2/2, and the amount of energy stored on the node is also CLVDD2/2. This later amount of energy is dissipated when the node is discharged so in one cycle the total energy dissipated is CLVDD2. If the gate is operating at a frequency of f, the average dynamic power dissipation is f times this or f CLVDD2. You can refer to the course text for discussions of noise margins, fan in and fan out, and manufacturability. 6