University:
Massachusetts Institute of Technology
Course:
6.012 | Microelectronic Devices and Circuits
Academic year:

2021
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473

Pages:

18
Author:

Henry A

Lecture 21 - Multistage Ampliﬁers (I) Multistage Amplifiers November 22, 2005 Contents: 1. Introduction 2. CMOS multistage voltage ampliﬁer 3. BiCMOS multistage voltage ampliﬁer 4. BiCMOS current buﬀer 5. Coupling ampliﬁer stages Reading assignment: Howe and Sodini, Ch. 9, §§9.1-9.3 Key questions • How can one build a wide range of high-performance ampliﬁers using the single-transistor stages studied so far? • What are the most important considerations when assembling mulstistage ampliﬁers: – regarding interstage loading? – regarding interstage biasing? 1. Introduction Ampliﬁer requirements are often demanding: • must adapt to speciﬁc kinds of signal source and load, • must deliver suﬃcient gain Single-transistor ampliﬁer stages are very limited in what they can accomplish ⇒ multistage ampliﬁer. VDD signal source RS signal load + vs vOUT RL VS VSS Issues: • What amplifying stages should be used and in what order? • What devices should be used, BJT or MOSFET? • How is biasing to be done? 2 Summary of single stage characteristics: stage CS CD Avo , Gmo , Aio Rin Rout Gmo = gm ∞ ro //roc transcond. amp. ∞ 1 gm +gmb voltage buﬀer current buﬀer Avo gm gm +gmb key function CG Aio −1 1 gm +gmb roc //[ro (1 + gm RS )] CE Gmo gm rπ ro //roc transcond. amp. CC Avo 1 rπ + β(ro //roc //RL ) 1 gm voltage buﬀer CB Aio −1 1 gm + RS β roc //{ro [1 + gm (rπ //RS )]} current buﬀer 2 Key diﬀerences between BJT’s and MOSFETs: BJT IB = IβC gm = ro = qIC kT VA IC MOSFET IG = 0 � > gm = 2 WL µCoxID > ro = 1 λID 2. CMOS multistage voltage ampliﬁer 2 Goals: • high voltage gain • high Rin • low Rout 2 Good starting point: CS stage RS ro//roc + + vs - vin - + + - -gm(ro//roc)vin vout • Rin = ∞ • Avo = −gm(ro //roc ), probably insuﬃcient • Rout = ro//roc, too high - RL 2 Add second CS stage to get more gain: RS + + + vs ro2//roc2 ro1//roc1 + vin1 - - - + + -gm1(ro1//roc1)vin1 vout1=vin2 - -gm2(ro2//roc2)vin2 vout2 - - • Rin = ∞ • Avo = gm1(ro1 //roc1 )gm2 (ro2 //roc2 ) • but Rout = ro2//roc2 , still high 2 Add CD stage at output: + vs + − 1 gm3 + gmb3 ro2 ⎢⎢roc2 RS + + vin + − − Avovin + −v vout gm3 in3 gm3 + gmb3 − vin3 − CS − CS RL CD • Rin = ∞ m3 • Avo = gm1(ro1 //roc1 )gm2 (ro2 //roc2 ) gm3g+g mb3 • Rout = 1 , gm3 +gmb3 now small , still high RL 3. BiCMOS multistage voltage ampliﬁer 2 Avo (CE) > Avo (CS) because ro(BJ T ) > ro(M OSF ET ) and gm (BJ T ) > gm(M OSF ET ) but... CS stage is best ﬁrst stage, since Rin = ∞. 2 Add CE stage following CS stage? + vs + − ro2 ⎢⎢roc2 ro1 ⎢⎢roc1 RS vin1 + − − Avo1vin1 + vin2 + rπ2 − CS + − Avo2vin2 vout RL − CE Trouble is interstage loading degrades gain: Rout1 = ro1 //roc1 Rin2 = rπ2 Voltage divider between stages: rπ2 rπ2 Rin2 = 1 Rout1 + Rin2 ro1 //roc1 + rπ2 ro1 //roc1 Additional gain provided by CE stage more than lost in interstage loading. 2 Use two CS stages, but add CC stage at output: ro2 ⎢⎢roc2 1 gm3 + β3 ro2 ⎢⎢roc2 RS + vs + − vin + − Avo1Avo2vin + + vin3 rπ3 + β3(ro3 ⎢⎢roc3 ⎢⎢RL) − + − vin3 vout RL − − CS − CS CC Interstage loading: Rout2 = ro2//roc2 , Rin3 = rπ3 + β3(ro3 //roc3 //RL) Then, interstage loss: rπ3 + β3(ro3 //roc3 //RL ) Rin3 = Rout2 + Rin3 ro2 //roc2 + rπ3 + β3(ro3 //roc3 //RL) better than trying to use a CE stage, but still pretty bad. Beneﬁt is that Rout has improved: Rout = Rout3 = 1 gm3 + Rout2 1 ro2 //roc2 = + β3 gm3 β3 Since, in general, gm (BJ T ) > gm (M OSF ET ), Rout could be better than CD output stage if ro2//roc2 is not too large. Otherwise, CD stage output is better. 2 Better voltage buﬀer: cascade CC and CD output stages. What is best order? Since Rin(CD) = ∞, best to place CD ﬁrst: + + vs + − vin + − 1 1 gm4 + β (g + g ) 4 m3 mb3 1 gm3 + gmb3 ro2 ⎢⎢roc2 RS + − Avo1Avo2vin vin3 − + + vin3 vin4 rπ4 + β4(RL ⎢⎢ro4 ⎢⎢roc4) − − CS − CS + − vin4 vout − CD − CC Interstage loading: Rin3 =1 Rout2 + Rin3 Rin4 = Rout3 + Rin4 rπ4 + β4(ro4 //roc4 //RL) 1 1 + rπ4 + β4(ro4//roc4 //RL ) gm3 +g mb3 and excellent output resistance: Rout = Rout4 = 1 gm4 + Rout3 1 1 = + β4 gm4 β4(gm3 + gmb3 ) RL 4. BiCMOS current buﬀer 2 Goals: • Unity current gain • very low Rin • very high Rout Start with common-base stage: iout iin is RS 1/gm -iin roc//(βro) RL • Aio = −1 • Rin = 1 gm • Rout = roc//{ro [1 + gm(rπ //RS )]} Note that if RS is not too low, Rout roc //(βro). Can we further increase Rout by adding a second CB stage? 2 CB-CB current buﬀer: iin1 is RS iout iin2 1 gm1 −iin1 β1ro1 ⎢⎢roc1 1 gm2 CB −iin2 RL CB [ gm2ro2(rπ2 ⎢⎢β1ro1 ⎢⎢roc1)] ⎢⎢roc2 Now Rout = Rout2 = roc2 //{ro2 [1 + gm2 (rπ2 //Rout1 )]} Plugging in Rout1 roc1//(β1 ro1 ), Rout = roc2//{ro2 [1 + gm2 (rπ2 //roc1 //β1 ro1)]} But, since rπ2 roc1 //(β1 ro1), then Rout roc2 //[ro2 (1 + gm2rπ2 )] roc2 //(β2ro2 ) Did not improve anything! The base current limits the number of CB stages that improve Rout to just one. Since CG stage has no gate current, cascade it behind CB stage. 2 CB-CG current buﬀer: iin1 is RS iout iin2 1 gm1 −iin1 β1ro1 ⎢⎢roc1 CB 1 gm2 −iin2 RL CG [gm2ro2(β1ro1 ⎢⎢roc1)] ⎢⎢roc2 Rout = Rout2 = roc2//[ro2 (1 + gm2 Rout1 )] with Rout1 roc1 //(β1 ro1), Rout = roc2 //[ro2 gm2 (roc1 //β1ro1 )] Now Rout has improved by about gm2ro2 , but only to the extent that roc2 is high enough... 5. Coupling ampliﬁer stages 2 Capacitive coupling Capacitors of large enough value behave as AC short, so signal goes through but bias is independent for each stage. Example, CD-CC voltage buﬀer: 5.0 V 5.0 V 3.2 V 4.0 V 2.5 V ISUP1 2.5 V ISUP2 Assumes VBE = 0.7 V VGS = 1.5 V • Advantages: – can select bias point for optimum operation – can select bias point close to middle of rails for maximum signal swing • Disadvantages: – to approximate AC short, need large capacitors that consume signiﬁcant area 2 Direct coupling: share bias points across stages. Example, CD-CC voltage buﬀer: 5.0 V 5.0 V 3.2 V 4.7 V 2.5 V ISUP1 ISUP2 Assumes VBE = 0.7 V VGS = 1.5 V • Advantages: – no capacitors: compact • Disadvantages: – bias point shared: constrains design – bias shifts from stage to stage and can stray too far from center of range Solution: use PMOS CD stage: 5.0 V 5.0 V ISUP1 3.2 V 2.5 V 1.7 V ISUP2 Assumes VBE = 0.7 V VGS = 1.5 V Trade-oﬀ: gm(PMOS)< gm (NMOS) → higher Rout In BiCMOS voltage ampliﬁer: Rout = 1 gm4 1 + β4(gm3 + gmb3 ) 2 Summary of DC shifts through ampliﬁer stages: Transistor Type Amplifier Type NMOS PMOS npn pnp V+ V+ V+ V+ IN iSUP Common Source/ Common Emitter (CS/CE ) iSUP OUT OUT IN IN iSUP V− V+ V− V+ IN iSUP OUT OUT iSUP V− V+ V− V+ IN iSUP OUT Common Gate/ Common Base (CG/CB) OUT OUT OUT iSUP IN V− V+ iSUP IN V− V+ V− V+ IN Common Drain/ Common Collector (CD/CC ) IN iSUP V− V+ iSUP IN OUT OUT OUT OUT IN IN iSUP iSUP V− V− V− V− Important diﬀerence in bias shift between stages in BJT and MOSFET amps: • In BJT (for npn): VBE VBE,on rather independent of transistor size and current level. • In MOSFET (for nMOSFET): VGS � � � � � � � 2ID L = VT + µnCox W Can be engineered through bias current and transistor geometry. 5.0 V 5.0 V 3.2 V 4.7 V 2.5 V ISUP1 ISUP2 Assumes VBE = 0.7 V VGS = 1.5 V Key conclusions • To achieve ampliﬁer design goals, several stages often needed. • In multistage ampliﬁers, diﬀerent stages used to accomplish diﬀerent goals: – voltage gain: common-source, common emitter – voltage buﬀer: common-drain, common collector – current buﬀer: common-gate, common base • In multistage ampliﬁers must pay attention to interstage loading to avoid unnecessary losses. • In direct-coupled ampliﬁers, bias is shared between adjoining stages: – must select compromise bias, – must pay attention to bias shift from stage to stage.

Lecture 21 - Multistage Amplifiers (I): Multistage Amplifiers

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