University:
Massachusetts Institute of Technology
Course:
6.012 | Microelectronic Devices and Circuits
Academic year:

2020
Views:

437

Pages:

6
Author:

shalashaska240

Recitation 13 Propagation Delay, NAND/NOR Gates 6.012 Spring 2009 Recitation 13: Propagation Delay, NAND/NOR Gates Outline • Propagation Delay for CMOS Inverters • Why NAND Gate is preferred over NOR Gate? • Design Project Propagation Delay for CMOS Inverters Figure 1: Discharging cycle: tPHL , Charging cycle: tPLH 1 (tPLH + tPHL ) 2 Charge(tobecharged/discharged) t = ; (Charging/Discharging)Current tPLH = ? charging through PMOS 1 2 CL VDD tPLH = wp Propagation time = we treat CL as a linear constant capacitor 2Lp μp Cox (VDD +VTp )2 why 12 ? tp is the time to discharge half of initial Q or charge half of ﬁnal Q tPHL = ? discharging through NMOS 1 CL VDD 2 CL VDD tPHL = wn = 2 kn (VDD − VTn )2 2Ln μn Cox (VDD − VTn ) As seen, tp ∝ L. This means, the longer the devices, the slower they become. This gets us to why NAND gates are preferred. 1 Recitation 13 Propagation Delay, NAND/NOR Gates 6.012 Spring 2009 NAND vs. NOR Gets us to why NAND gates are preferred: n+ region is highly doped no resistance This is exactly like the following: Eﬀective length of two n-channel devices in series Leﬀ = 2Ln For symmetrical transfer characteristics, tPLH = tPHL μn = 2μp Leﬀ n = 2Lp ∴ wn = wp But since μn = 2μp , we are better oﬀ having the series connection in NAND (rather than 2 Recitation 13 Propagation Delay, NAND/NOR Gates 6.012 Spring 2009 NOR where PMOS’s are in series). If we wanted the same thing in NOR: μn = 2μp Leﬀ p = 2Leﬀ n ∴ wp = 4wn NOR Structure So for NAND: w L For M-input NAND: = w L n w L = n Reason is? p M w 2 L p M-input NAND has M-NMOS’s in series =⇒ Leﬀ = M Ln . So, for kneﬀ = kpeﬀ : wn × μn M Ln μn wn ×2 M Ln w n L n wp μp Lp = 2μp wp = Lp M w = 2 L p = 3 Recitation 13 Propagation Delay, NAND/NOR Gates 6.012 Spring 2009 CL =? Assume the next stage is another inverter. CL is all capacitances seen at node Vout . CL = Cgstage2 + Cdbp1 + Cdbn1 Cgstage2 Cgn2 CdbM = Cgp2 + Cgn2 2 Cox (wL)n2 + Cox wn2 = 3 ≈ Cox (wL)n2 = Cjn1 (wLdiﬀ )n1 + Cjswn1 (w + 2Ldiﬀ )n1 =⇒ CL = Cox (wL)n2 + Cox (wL)p2 + Cjn1 (wLdiﬀ )n1 + Cjswn1 (w + 2Ldiﬀ )n1 + Cjp1 (wLdiﬀ )p1 + Cjswp1 (w + 2Ldiﬀ )p1 4 Recitation 13 Propagation Delay, NAND/NOR Gates 6.012 Spring 2009 Design Project What is the use of the circuit? Light in =⇒ width modulated electrical signal out. What does each stage do? • N1 : charging 1,2 capacitors with Ilight + Ibias • At TM : tipping point, Vout changes from High to Low =⇒ say VM,1 = 1 V VM,2 = 2 V • Final stage: driver stage You need enough current to be able to charge CL quickly enough to meet tr and tf of specs. Decide how many stages you need (remember Vout positive pulse we need), and think about ratio of sizing between stages (hint: between 3 − 6 is the answer) 5 Recitation 13 Propagation Delay, NAND/NOR Gates 6.012 Spring 2009 Speciﬁcations • Vout : tr , tf 3 ns • Minimum gate areas • At least 20 ns distinction between pulse widths corresponding to diﬀerent Ilight levels of 0, 1, 2, 3, μA • Report: what should you submit Q & A about design problem 6