University:
Massachusetts Institute of Technology
Course:
6.012 | Microelectronic Devices and Circuits
Academic year:

2021
Views:

265

Pages:

20
Author:

paychiashf80

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 2005 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS inverter with current-source pull-up 3. Complementary MOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, §5.3 Key questions • What are the key design trade-offs of the NMOS inverter with resistor pull-up? • How can one improve upon these trade-offs? • What is special about a CMOS inverter? 1. NMOS inverter with resistor pull-up (cont.) V+=VDD VOUT=VDS VOH=VMAX=VDD R IR slope= Av(VM) VOUT=VIN VOUT VM ID VIN CL VOL=VMIN 0 0 VT VDD VM VIL VIN=VGS VIH 2 Noise margins: N ML = VIL − VOL = VM − N MH = VOH −VIH VM AX − VM − VM IN |Av (VM )| VM IN 1 = VM AX −VM (1+ )+ |Av (VM )| |Av (VM )| Need to compute |Av (VM )|. Small-signal equivalent circuit model at VM (transistor in saturation): R D G + + vin vgs - - + gmvgs ro vout - S + + vin gmvin ro//R - vout - vout = −gm vin(ro//R) Then: Av = vout = −gm(ro //R) ' −gm R vin Then: |Av (VM )| = gm (VM )R From here, get N ML and N MH using above formulae. 2 Dynamics • CL pull-down limited by current through transistor [will study in detail with CMOS] • CL pull-up limited by resistor (tP LH ∼ RCL) • pull-up slowest VDD VDD R R VOUT: LO HI VOUT: HI LO VIN: LO HI CL pull-down VIN: HI LO CL pull-up 2 Inverter design issues: noise margins ↑ ⇒ |Av | ↑ ⇒ • R ↑ ⇒ RCL ↑ ⇒ slow switching • gm ↑ ⇒ W ↑ ⇒ big transistor (slow switching at input) Trade-off between speed and noise margin. During pull-up, need: • high current for fast switching, • but also high resistance for high noise margin. ⇒ use current source as pull-up. 2. NMOS inverter with current-source pull-up I-V characteristics of current source: iSUP + vSUP 1 roc ISUP iSUP _ 0 0 vSUP Equivalent circuit models: iSUP + vSUP ISUP roc roc _ large-signal model small-signal model • high current throughout voltage range: iSU P ' ISU P • high small-signal resistance, roc. NMOS inverter with current-source pull-up: load line VDD iSUP=ID VGS=VDD iSUP ISUP VGS=VIN VOUT VIN CL VGS=VT 0 0 VDD Transfer characteristics: VOUT VDD 0 0 VT High roc ⇒ high noise margin VDD VIN VDS Dynamics: VDD VDD iSUP iSUP VOUT: HI LO VIN: LO HI CL pull-down VOUT: LO HI VIN: HI LO CL pull-up Faster pull-up because capacitor charged at constant current. 2 PMOS as current-source pull-up I-V characteristics of PMOS: S G IDp D -IDp -IDp saturation VSGp VSGp=-VTp 0 0 0 VSDp 0 -VTp Note: enhancement-mode PMOS has VT p < 0. In saturation: −IDp ∝ (VSG + VT p )2 VSGp Circuit and load-line diagram of inverter with PMOS current source pull-up: VDD PMOS load line for VSG=VDD-VB -IDp=IDn VDD VB VOUT VIN VIN CL 0 0 VDD Transfer function: NMOS cutoff PMOS triode VOUT NMOS saturation PMOS triode VDD NMOS saturation PMOS saturation NMOS triode PMOS saturation 0 0 VTn VDD VIN VOUT Noise margin: • compute VM = VIN = VOU T • compute |Av (VM )| At VM both transistors saturated: IDn = −IDp = Wn µnCox (VM − VT n )2 2Ln Wp µp Cox(VDD − VB + VT p )2 2Lp And: IDn = −IDp Then: VM = VT n + v u u u u u u u t p µp W Lp Wn (VDD µ n Ln − VB + VT p ) Small-signal equivalent circuit model at VM : S2 + gmpvsg2 vsg2=0 - + vin - rop G2 D2 G1 + D1 + vgs1 gmnvgs1 ron - vout - S1 + vin + gmnvin ron//rop - vout - Av = −gmn (ron//rop ) NMOS inverter with current-source pull-up allows fast switching with high noise margins. But... when VIN = VDD , there is a direct current path between supply and ground ⇒ power consumption even if inverter is idling. VDD PMOS load line for VSG=VDD-VB -IDp=IDn VDD VB VOUT:LO VIN:HI VIN CL 0 0 VDD VOUT Would like to have current source that is itself switchable, i.e., it shuts off when input is high ⇒ CMOS! Screen shots of NMOS inverter transfer characteristics: 2 NMOS inverter with resistor pull-up 2 NMOS inverter with current source pull-up 3. Complementary MOS (CMOS) Inverter Circuit schematic: VDD VIN VOUT CL Basic operation: •VIN = 0 ⇒ VOU T = VDD VGSn = 0 < VT n ⇒ NMOS OFF VSGp = VDD > −VT p ⇒ PMOS ON •VIN = VDD ⇒ VOU T = 0 VGSn = VDD > VT n ⇒ NMOS ON VSGp = 0 < −VT p ⇒ PMOS OFF No power consumption while idling in any logic state. Output characteristics of both transistors: IDn -IDp VGSn VSGp VGSn=VTn VSGp=-VTp 0 0 0 VDSn 0 VSDp Note: VIN = VGSn = VDD − VSGp ⇒ VSGp = VDD − VIN VOU T = VDSn = VDD − VSDp ⇒ VSDp = VDD − VOU T IDn = −IDp Combine into single diagram of ID vs. VOU T with VIN as parameter. VDD ID VIN VOUT VDD-VIN VIN CL 0 0 VOUT ? no current while idling in any logic state. Transfer function: NMOS cutoff PMOS triode VOUT NMOS saturation PMOS triode VDD NMOS saturation PMOS saturation NMOS triode PMOS saturation NMOS triode PMOS cutoff 0 0 VTn VDD+VTp VDD VIN ? ”rail-to-rail” logic: logic levels are 0 and VDD ? high |Av | around logic threshold ⇒ good noise margins Transfer characteristics of CMOS inverter in WebLab: Key conclusions • In NMOS inverter with resistor pull-up: trade-off between noise margin and speed. • Trade-off resolved using current-source pull-up: use PMOS as current source. • In NMOS inverter with current-source pull-up: if VIN = HI, power consumption even if inverter is idling. • Complementary MOS: NMOS and PMOS switch alternatively ⇒ – no power consumption while idling – ”rail-to-rail” logic: logic levels are 0 and VDD – high |Av | around logic threshold ⇒ good noise margins