6.013 Electromagnetics and Applications, Problem Set 6 Solutions

6.1 Problem 6.1 GIVEN Infinitely-long stripline for which d = 1 µm and the medium between the plates has µ = µ0 and � = 4�0 . 6.1.1 FIND Width, W , for which the characteristic impedance of the line is 50 Ω. Discuss whether ideal parallel plate model is valid for these dimensions. WORK For an ideal parallel plate transmission line, Z0 = ηd/W , � where η � is the characteristic impedance of the medium (for EM waves). As before, η = µ/� = µ0 /(4�0 ) = η0 /2 = 188.5 [Ω]. Then the inverse problem is solved as W = dη/Z0 = 1 × 188.5/50 = 3.77 [µm] . Since W/d = 3.77, it is acceptable to approximate the line as an ideal parallel plate config uration to first order, but we should not expect very accurate results. 6.1.2 FIND For a 1 V DC step signal, what is the intensity, I, (time average Poynting vector magnitude [W]) of the TEM field propagating between the plates? WORK For the parallel plate waveguide, the electric field runs from top to bottom plate and has magnitude, E = V /d = 106 [V/m]. Then the time-average Poynting vector is found from �S� = |E 2 /(η)| = 1012 /188.5 = 5.305 × 109 W/m2 . There is no factor of because the signal is a step and not a sinusoid. Multiplying by the cross-sectional area I = �S�A = �S�W d = �S�d2 W/d = �S�d2 η/Z0 . 2 = |E 2 /(η)|d2 η/Z0 = (Ed)2 /(Z0 ) = v+ /(Z0 ) = 1/50 = 0.02 [W] (6.1) Even though we derived this for the parallel plate geometry, it is general for TEM lines (and will work for sinusoids after including the factor of ). Let’s check the magnetic field. It can be found by drawing an Ampèrian loop, C encircling a single strip of�the line, and noting that the field is much stronger between the plates than � · d�l = Ienc ≈ HW =⇒ H = I/W . For a single pulse, v+ and i+ are outside. Then C H related by v+ = Z0 i+ , so i+ = v+ /Z0 = 1/50 = 0.02 [A], and H = I/W = 0.02/3.77×10−6 ∼ = 3 9 2 � � � 5.305 × 10 [A/m]. But �S � = E × H = ẑ5.305 × 10 W/m , which is exactly what we got before. 7 6.1.3 FIND Evaluate the time average electric and magnetic energy densities per meter, We� and Wm� [J/m]. WORK The fields were determined in the previous section. The energy density stored in the electric field is �E 2 /2; multiplying by the cross-sectional area gives the energy density per meter of the line, v2 �E 2 η d2 E 2 We� = W d =� = + 2 Z0 2 2Z0 c , (6.2) 8 −10 −11 = 0.01/(1.5 × 10 ) = (2/3) × 10 ≈ 6.67 × 10 [J/m] since c = (L� C � )−1/2 = (µ�)−1/2 = c0 /2. Likewise, for the magnetic energy, i2 Z0 v2 Z0 W 2 H 2 = + = + η 2 2c 2Z0 c , −11 ≈ 6.67 × 10 [J/m] Wm� = W dµH 2 /2 = µ −10 = (2/3) × 10 (6.3) the same as for the electric field, as expected. 6.1.4 FIND Show that the average power on the line, c(We� + Wm� ), is equal to the intensity, I, found in part (b). WORK The quantity, c(We� + Wm� ), is c(We� + Wm� ) = 2cWe� = 2c 2 v+ v2 = + . 2Z0 c Z0 (6.4) This is exactly what we got before. Note that this implies the phase velocity, c, is also the group velocity (the line is non-dispersive). In general, transmission lines are dispersive. 6.1.5 FIND Show 1. that for two arbitrary signals flowing in opposite directions, f+ (t−z/c) and f− (t+z/c), with v(z, t) = f+ + f− , the total power flowing down the line in the +ẑ direction at any (t, z) is the power flowing in +ẑ less the power flowing in −ẑ; 8 2. whether or not this superposition holds for two waves traveling in the same direction. WORK It is generally a good idea to apply superposition at the level of fields. In the transmission line problem, we get away with working in terms of voltage and current signals with the 2 convention that i+ = Z0 v+ , but i− = Z0 v− . We have seen that I+ = v+ /Z0 = v+ i+ . The same would be true if the subscript were permuted to −. If there are two signals on the line, we may apply superposition at the level of the voltage and current in the following way: 2 2 I+,net = (v+ + v− )(i+ − i− ) = (v+ + v− )(v+ − v− )/Z0 = (v+ − v− )/Z0 = I+ − I− , (6.5) which is what we set out to demonstrate. However, for two signals propagating in the same direction (and at the same phase velocity), I+,net = (v+,1 + v+,2 )(i+,1 + i+,2 ) = (v+,1 + v+,2 )(v+,1 + v+,2 )/Z0 . 2 2 = (v+,1 + v+,2 + 2v+,1 v+,2 )/Z0 = I+,1 + I+,2 + 2v+,1 v+,2 /Z0 (6.6) The cross-coupling term destroys the superposition of powers. Superposition is one of the defining features of linear field and wave phenomena. It can be a subtle topic at times and a source of confusion, as this problem demonstrates. But you can see your way through by applying some physical reasoning and a few simple rules. 9 6.2 Problem 6.2 GIVEN TEM line, � = 30 [cm], air-filled, Z0 = 100 [Ω], excited at one end by a matched voltage source, V (t), where V (t) is a step function 2u(t) volts. 6.2.1 FIND Sketch and quantitatively dimension V (z) and I(z) on the line at t1 = 15 × 10−10 [s] for the case where the load is a 300 [Ω] resistor. WORK Make the transformation, z � = z − �, so that at the load, z � = 0. If the line is filled with air, then c = c0 , and the propagation time across the line is τ = �/c = 0.3/3 × 108 = 10−9 [s]. This means that t = 15 × 10−10 [s] = 3�/(2c). This means the line voltage is � v(z � , t = t1 ) = v+ (1 + ΓL u((t − τ − z � /c))) = v+ (1 + ΓL u( + z � )). 2 (6.7) At t = 0, the source sees a voltage divider across the terminals of the line, so v+ = Vs /2 = 1 [V]. ΓL is the reflection coefficient at the load, ΓL = (ZL /Z0 − 1)/(ZL /Z0 + 1) = 1/2. As such, in terms of z, 1 � v(z, t = t1 ) = v+ (1 + ΓL u((t − τ − z � /c))) = 1 + u(z − ) . 2 2 (6.8) Since the source is matched, there will be no further reflections. As expected, the forward and reflected steps sum to the steady-state voltage of 3/2 [V]. The current is found from i(z � , t = t1 ) = v+ v+ � (1 − ΓL u((t − τ − z � /c))) = (1 + ΓL u( + z � )). Z0 Z0 2 (6.9) This is � 1 v(z, t = t1 ) = v+ (1 + ΓL u((t − τ − z � /c))) = 1 + u(z − ) . 2 2 Figure 6.1 shows the voltage and current distributions on the line. 6.2.2 FIND Repeat for the case when the load is a capacitor with C = 2 × 10−12 [F]. 10 (6.10) [s]) [V] −10 V(z,t=15×10 i(z,t=15×10−10 [s]) [A] 1.5 1 0.5 0 0 5 10 15 z [cm] 20 25 30 0 5 10 15 z [cm] 20 25 30 0.01 0.005 0 Figure 6.1: Current and voltage distribution at 3�/(2c) for 300 Ω load. 11 WORK The approach to take here is to replace the line to the left of the load with its Thévenin equivalent circuit. This has a source of vth = 2v+ u0 (t − �/c) and a source impedance of Z0 = 100 Ω. The circuit equations lead to vth − vc dvc d(vc − vth ) = ic = C =C Z0 dt dt vc − vth d(vc − vth ) = =− dt Z0 C iR = (6.11) This is a first-order ordinary differential equation, and we write the solution by inspection, vc − vth = V0 e−t/(Z0 C) u(t − �/c) ⇒ vc = 2v+ (1 − e−t/(Z0 C) )u(t − �/c), (6.12) where we were able to factor out vth = 2v+ because of the initial condition that the capacitor is a short. The next step is to determine how this load voltage translates into waves on the line. The load voltage is the sum of the forward and backward waves, vc = v+ + v− = 2v+ (1 − e−t/(Z0 C) )u(t − �/c). Let t� ≡ t − �/c and solve this relation for v− : � v− (z � = 0, t) = v+ (1 − 2e−t /(Z0 C) )u(t� ) (6.13) Lastly, we must make this wave travel in the −ẑ-direction: � � � t + z � /c � v− (z , t) = v+ (1 − 2 exp − )u(t� + z � /c) (6.14) Z0 C Let us make the transformation to the problem coordinates, z � = z − � and t� = t − �/c, and add in v+ : � � t + (z − 2�)/c vt (z, t) = v+ + v= v+ + v+ u(t + z/c − 2�/c)(1 − 2 exp − ). Z0 C (6.15) The current problem is solved similarly: � � � v+ t + z � /c i− (z , t) = (1 − 2 exp − )u(t� + z � /c), Z0 Z0 C � so � � v+ v+ z − 2� t + (z − 2�)/c it (z, t) = i+ − i− = + u(t + ). )(1 − 2 exp − Z0 Z0 c Z0 C and note that v+ = 1 V , as before. Figure 6.2 illustrates the solution. 12 (6.16) (6.17) [s]) [V] −10 V(z,t=15×10 i(z,t=15×10−10 [s]) [A] 2 1.5 1 0.5 0 0 5 10 15 z [cm] 20 25 30 0 5 10 15 z [cm] 20 25 30 0.02 0.015 0.01 0.005 0 Figure 6.2: Current and voltage distribution at 3�/(2c) for capacitive load with C = 2 × 10−12 F. 13 v(z,t=3D/(2c)) i(z,t=3D/(2c)) 2 1 0 0 0.5 z/D 1 0.5 z/D 1 0.02 0.01 0 0 Figure 6.3: Current and voltage distribution at 3�/(2c). 6.2.3 FIND Repeat for the case when the load is a diode triggering at 1 V (i.e. an ideal diode back-biased by a 1 V battery). WORK This problem is amenable to either the “bounce” approach we used in part (a) or the Thévenin equivalent circuit used in part (b). We could also work backwards. In the steadystate, the voltage on the line will be unity if the diode is shorted, while the current will be (2-1) V/100 Ω = 0.01 A (since there is no voltage differential on the line). And we cannot have reflections at the source. As such, we can be sure that the diode will reach its threshold on the first bounce, and indeed, it does: because v+ = 1 V, the diode will appear as a short. Now, since we short voltage sources, ΓL = −1, and v− = −v+ . So how do we arrive at the steady state solution? The answer is that another wave will be launched when the diode becomes a short, again of height, 1 V. This precisely cancels out the effect of the reflected wave, so that the system actually reaches steady-state in minimum time. At t = 3�/(2c), v(z, t1 ) = 1 [V] and i(z, t) = 0.01 [A] . Figure 6.3 illustrates the solution. 14 6.3 Problem 3 GIVEN A line driver at one end of a 2 cm-long, Z0 = 200 Ω TEM transmission line triggers a flip-flop at the other end with a step function, as illustrated. The dielectric in the line has � = 4�0 and µ = µ0 . The input to the flip-flop can be treated as a 50 Ω load; it triggers (changes the output state of the flip-flop) at 4 V. 6.3.1 FIND Sketch and dimension v(t, z) on the line at t = 0.1 ns (10−10 s). WORK The time required √ for a signal to traverse the length of the line is τ = �/c. � = 0.02 [m] and √ c = 1/ µ� = 1/ µ0 4�0 = c0 /2. As such, τ = 2 × 10−2 /(3 × 108 /2) = (4/3) × 10−10 s. If t = t1 = 10−10 = (3/3) × 10−10 s, the signal will have reached 3/4 of the way down the line. As such, the first reflection, v− , will not have been generated yet. v+ is found from a voltage divider at the source: v+ = Vs 200/(50 + 200) = 4Vs /5 = 4 × 10/5 = 8 [V]. As such, the voltage distribution will be � v+ = 8 [V] for 0 ≤ z < 3�4 v(z) = (6.18) 0 for 3�4 ≤ z ≤ �, with � = 2 [cm]. Figure 6.4 illustrates the voltage distribution for parts (a) and (b). 6.3.2 FIND Repeat (a) for t=0.2 ns. WORK: Now, with t = t2 = 2 × 10−10 [s], the signal will have travelled another 3�/4. This means it reaches the load after travelling a distance, �/4, and then a reflection travels �/2 back toward the source. Let’s examine the reflection. The reflection coefficient at the load is ΓL ≡ v− ZL − Z0 ZL,n − 1 = = , v+ ZL + Z0 ZL,n + 1 (6.19) where ZL,n is the load impedance normalized by the characteristic impedance of the line, Z0 . This ratio is ΓL = (0.25 − 1)/(0.25 + 1) = (−3/4)/(5/4) = −3/5. 15 10 v(z) [V] 8 6 4 2 t=0.1 ns t=0.2 ns 0 0 0.5 1 z [cm] 1.5 2 Figure 6.4: Voltage distribution for parts (a) and (b) of problem 6.3. Since v+ = 8 V, v− = ΓL v+ = −3 × 8/5 = −4.8 V. The total voltage is the sum of the forward and backward waves. This results in v(z) = � v+ = 8 [V] for 0 ≤ z < �/2 v+ + v− = 8 − 4.8 = 3.2 [V] for �/2 ≤ z ≤ �, (6.20) with � = 2 [cm]. Figure 6.4 illustrates the voltage distribution for parts (a) and (b). 6.3.3 FIND Sketch quantitatively the load voltage, vL (t), until the flip-flop is triggered; its trigger voltage is 4 V. Note that triggering is excessively delayed. WORK The load will see step increments every 2τ = 2�/c time interval, starting at t = �/c. The first step is from zero (the assumed initial condition on the line) to vL,1 = v+,1 + v−,1 , which we already saw yielded 3.2 V. The second step will include the second forward and backward 16 reflections, vL,2 = vL,1 + v+,2 + v−,2 . vL,1 and all other signal persist because the source is a step. You can think of the problem also as applying to infintesimal pulses from the source; each one traverses the line, is reflected at the load, goes back to the source and is reflected again, and so forth. The source puts out a continuous supply of these infinitesimal pulses because it is a step. The next two reflections are found as before. Define the source reflection coefficient analogously with that at the load, ΓS = (Zs − Z0 )/(Zs + Z0 ). For this problem, since Zs = ZL , ΓS = ΓL = −3/5. Then v+,2 = ΓS v−,1 = ΓS ΓL v+,1 = 9 × 8/25 = 2.88 [V], while v−,2 = ΓL v+,2 = ΓL ΓS ΓL v+,1 = −27 × 8/125 = −1.728 [V]. Then vL,2 = v+,1 + v−,1 + v+,2 + v−,2 = 8 − 4.8 + 2.88 − 1.728 = 4.352 [V]. This is above the trigger voltage, so the flip-flop triggers at 3τ = 4 × 10−10 [s]. In general, the nth -step load voltage occurs at time t = (2n − 1)τ , and has step height, vL |(2n−1)τ ≤t<2nτ = n � v+,i + v−,i = i=1 = (1 + ΓL ) n � v+,i (1 + ΓL ) i=1 n � (ΓL ΓS ) i−1 v+,1 i=1 = v+,1 (1 + ΓL ) n−1 � = v+,1 (1 + ΓL ) (ΓL ΓS )i , (6.21) i=0 1 − (ΓL ΓS ) 1 − ΓL ΓS n where we have summed the geometric series. For n → ∞, this geometric series results in vL,t→∞ = v+,1 (1+ΓL ) /1 (1−ΓL ΓS ) = VS ZSZ+0Z0 (1+ΓL )/(1−ΓL ΓS ). Algebra will show that this L is vL,t→∞ = VS ZSZ+Z = vL,ss , as expected. In this case, with VS = 10 V and ZS = ZL = 50 L Ω, vL,ss = 5 [V], above the trigger voltage. However, after interval, τ , at which time the load sees the first pulse, the load voltage is 3.2 V, and the flip-flop will not trigger, but will suffer at least another two bounce intervals. Figure 6.3.3 shows the voltage trace for the load. 6.3.4 FIND Load voltage as t → ∞. WORK We already determined this limit in the last section. It was vL (t → ∞) = 5 [V] . This corresponds to a voltage divider between the load and source impedances. It underscores the lessons that transmission lines are wires, and in the steady state, after the transient has decayed, they may be treated like circuit nodes, just as we have always treated them prior to learning about transmission lines in 6.013. 17 5 v [V] 4 3 2 vL 1 v 0 0 0.5 t [s] 1 trig,ff −9 x 10 Figure 6.5: Load voltage trace. Triggering occurs when load voltage exceeds flip-flop trigger voltage (here, 4 × 10−10 [s]). 18 FIND If the line impedance is matched at 50 Ω, would there still be excessive delay? WORK Matching the line impedance to the source and load eliminates reflections. We achieve the steady-state result with the first traversal of the line, so that vL = 0, V, t < τ , and 5V , t ≥ τ . Since the load triggers at 4 V, the system achieves the minimum possible delay between firing the signal at the source and getting a result at the (flip-flop) load. This is one of the many reasons why understanding transients on transmission lines is important. A flip-flop is a bit in digital memory, the source, an attempt to change that bit’s state. Matching impedances increased the speed of this memory circuit by a factor of three. 6.3.5 FIND Write a simple equation for v(z, t) valid for 0 < t < 0.1 ns, then extend it to 0.2 ns. WORK z−� z − 2� ) = v+,1 u(t − z/c) + v−,1 u(t + ) c c (6.22) where v+,1 = VS Z0 /(ZS + Z0 ) = 8 [V] , v−,1 = ΓL v+,1 = −4.8 [V] and u(x) is the unit step function (also called “Heaviside” step function, after Oliver Heaviside, a pioneer of the application of Maxwell’s equations to transmission lines). This summation can be continued, resulting in a similar expression as obtained for the load voltage trace earlier. The differences are that now, a phase contribution from posi tion will also occur, and also, there will be two steps per each 2τ interval instead of one, corresponding to the appearance of the forward and backward edge at a particular location. v(z, t) = v+,1 u(t − z/c) + v−,1 u(t − τ + 19 6.4 Problem 4 GIVEN Unit-step current source drives given circuit (transmission line of length, D, with Z0 and c, terminated in two more transmission lines in parallel, each of infinite length and same Z0 , c). 6.4.1 FIND Sketch and dimension the voltage on all lines at time, 1. t = t1 = D/(2c), 2. t = t2 = 3D/(2c), and 3. t = t3 = 5D/(2c). WORK For this problem, it is more convenient to begin by studying the current problem. In the steady state, we expect 1 A to flow down the main line, and A to flow down each of the parallel branches. At z = D, there will be a reflection because of an impedance mismatch. The look-in impedance for the parallel branches is simply the parallel combination of their characteristic impedances, ZD = Z0 ||Z0 = Z0 /2. The voltage reflection coefficient is then ΓD = ZD,n − 1 1/2 − 1 1 = =− . ZD,n + 1 1/2 + 1 3 (6.23) The voltage reflection coefficient at the source is trickier. But remember that when we superimpose the contribution from different sources (including incoming signals), we short all other voltage sources and open all other current sources. Then the reflected signal sees the current source as an open circuit, which means that the source voltage reflection coefficient is Γs = 1. Now, the first current signal edge, i+,1 , will have height, 1 A, since the source is a unit step. The reflection will be i1 = −ΓD i+,1 , where the negative sign appears because i+ = v+ /Z0 but i− = −v− /Z0 , and v− = ΓD v+ . After t = 2D/c, there will be another reflection at the current source, with i+,2 = −Γs i−,1 = Γs ΓD i+,1 . Putting these pieces together gives the following line current for 0 ≤ t < (6D/(2c) = 3D/c): i(z, 0 ≤ t < 3D/c) = i+,1 � � z − 2D z + 2D u(t − z/c) − ΓD u(t + ) + Γs ΓD u(t − ) . (6.24) c c 20 Noting again that v+ = i+ Z0 but v− = −i− Z0 allows for the transformation to voltage: � � z − 2D z + 2D v(z, 0 ≤ t < 3D/c) = Z0 i+,1 u(t − z/c) + ΓD u(t + ) + Γs ΓD u(t − ) . c c (6.25) We can now simply evaluate this expression at the three given time snapshots:   Z0 i+,1 u((D/2) − z) t = t1 = D/(2c)    Z0 i+,1 (1 + ΓD u(z + (3D/2) − 2D)) = Z0 i+,1 (1 + ΓD u(z − (D/2))) t = t2 = 3D/(2c) v(z) =  Z0 i+,1 (1 + ΓD + Γs ΓD u((5D/2) − z − 2D))   t = t3 = 5D/(2c)  = Z0 i+,1 (1 + ΓD + Γs ΓD u((D/2) − z)) (6.26) where i+,1 = 1 [A] , ΓD = −1/3 , and Γs = 1 . The formula derived in the last section for the load voltage may be used again after replacing ΓL with ΓD ; then the voltage at z = D as t → ∞ is vD (t → ∞) = Z0 i+,1 (1 + ΓD ) 1−Γ1S ΓD = Z0 i+,1 (2/3) 4/13 = v+,1 /2 Again, it is useful to interpret this steady-state result in terms of the current. In the steady state, we expect the current on each branch to be half of the current coming out of the source, A. A steady-state voltage at D, and everywhere else on the primary line from 0 ≤ z < D, of v+,1 /2 = Z0 i+,1 /2 produces exactly this branch current. This is only the voltage on the primary line, 0 ≤ z < D. The voltage on the branches is identical, since they are in parallel. Here, at time t = D/c, an identical voltage step will be launched down each of these lines of magnitude, vL = v+,1 (1 + ΓD ), so that the voltage on these branches for 0 ≤ t < 3D/c is � vb ranches(z � , 0 ≤ t < 3D/c) = Z0 i+,1 u(t − D/c − z � /c) (6.27) � , where z = 0 at z = D, and z measures the length along either of the branches. Evaluating at the three snapshots gives:   0 ≤ t = t1 = D/(2c) 0 � � � vbranches (z , t) = Z0 i+,1 u(3D/(2c) − D/c − z /c) = Z0 i+,1 u(D/2 − z ) 0 ≤ t = t2 = 3D/(2c) .   Z0 i+,1 u(5D/(2c) − D/c − z � /c) = Z0 i+,1 u(3D/2 − z � ) 0 ≤ t = t3 = 5D/(2c) (6.28) Figure 6.6 illustrates the solution at the three snapshots for both the primary and branch lines. 21 v(z,t)/(1A×Z0) 1 0.5 0 0 t=D/(2c)→ t=3D/(2c)← t=5D/(2c)→ 0.2 0.4 z/D 0.6 0.8 1 v(z,t)/(1A×Z0) 1 t1=D/(2c) 3t1→ 5t1→ 0.5 0 0 0.5 1 z/D [branch z] 1.5 2 Figure 6.6: Voltage distribution on the primary (top) and branch (bottom) lines. 22 6.5 Problem 5 GIVEN A current source delivering I0 drives a delicate transistor that has an input impedance of 4Z0 through a TEM line of impedance, Z0 . The system has reached a steady state. 6.5.1 FIND At t = 0, the switch at z = D/2 opens for a time interval, D/10c, and then recloses. Sketch the voltage, v(z), on the line at t = D/(5c). WORK The initial current distribution on the line is i(z, t < 0) = I0 . This requires the voltage distribution to be V0 ≡ v(z, t < 0) = I0 ZL = 4I0 Z0 . An intuitive way to think about this problem is that the switch sends a wave proclaiming that it has changed from a short to an open circuit it (“darn it”). At time, D/(10c), the switch sounds a counter-wave saying that it is now, again, a short (“darn it”). In the language of matching boundary conditions, this information is embodied by the statement that the current through an open circuit is zero. Since the current on the line is initially I0 , the switch sends a pulse, i− = −I0 travelling to the left of the open circuit, and another pulse, i+ = −I0 , traveling to the right. Each pulse lasts for a time, D/(10c), so that its length is D/10. Behind the pulse, the distributions return to their steady-state values. Then, with the transformations, v+ = Z0 i+ and v− = −Z0 i− , we have v+ = −Z0 I0 and v− = −(−Z0 I0 ) = Z0 I0 . This means that the total voltage on the left-moving pulse is vlef t = V0 +v− = 5Z0 I0 , while the total voltage on the right-moving pulse is vright = V0 +v+ = 3Z0 I0 . As such, we can write the total voltage everywhere on the line at time, t = D/(5c), as v(z, t = D/(5c)) = V0 + v− [u(z − 3D/10) − u(z − 4D/10)] + v+ [u(z − 6D/10) − u(z − 7D/10)] . (6.29) Figure 6.7 illustrates this voltage distribution. 6.5.2 FIND Will vL (t) ever exceed the transistor’s breakdown limit of 7Z0 I0 ? Explain. WORK At the load, the voltage reflection coefficient is ΓL = (ZL,n − 1)/(ZL,n + 1) = 3/5. At the source, remembering that for superposition problems, we short voltage sources and open current sources, we know that the current source appears as an open circuit, so that ΓS = 1. 23 0 0 v(z,t=D/(5c)) / (Z I ) 7 6 5 4 3 2 1 0 0 0.3 0.4 0.5 0.6 0.7 z/D 1 Figure 6.7: Voltage distribution on the line at time, t = D/(5c), after the switch was initially opened. 24 The load voltage will be smallest after the rightward-moving pulse, v+ , hits the load for the first time, since this pulse is beneath the initial voltage and ΓL = 3/5 > 0. It will be largest after the leftward-moving pulse, v− reaches the load. This will happen after it has reflected off of the source, where it suffers no loss because ΓS = 1, and then traverses the entire length of the line before reflecting at the load. All subsequent bounces for either pulse will have smaller pulses, as the pulse heights/depths will diminish by a factor of ΓL = 3/5 with each round trip. As such, we need only concern ourselves with a maximum load voltage of vL,max = V0 + v− (1 + ΓL ) = Z0 I0 (4 + 1 × (1 + 3/5)) = 5.6Z0 I0 < 7Z0 I0 . This is beneath the breakdown voltage of the transistor. Note that the period for which the load voltage reaches this height is D/(10c), the duration of the pulse. The minimum load voltage is vL,min = V0 + v+ (1 + ΓL ) = Z0 I0 (4 − 1 × (1 + 3/5)) = 2.4Z0 I0 , which also is (presumably) safe for the transistor. Again, this minimum voltage lasts for a duration of D/(10c). 25