Electric VHDL Mode: Major Mode for Editing VHDL Code

Electric VHDL mode: Major mode for editing VHDL code. Usage: ------ TEMPLATE INSERTION (electrification) (`SPC'): After typing a VHDL keyword and entering `SPC', you are prompted for arguments while a template is generated for that VHDL construct. Typing `RET' (or `C-g' in yes-no queries) at the first prompt aborts the current template generation. Typing `M-SPC' after a keyword inserts a space without calling the template generator. Automatic calling of the template generators (i.e. electrification) can be disabled (enabled) by setting the variable `vhdl-electric-mode' to nil (non-nil) or by typing `C-c C-e' (toggles electrification mode). Template generators can be called using the VHDL menu, the key bindings, or by typing the keyword (first word of menu entry not in parenthesis) and `SPC'. The following abbreviations can also be used: arch, attr, conc, conf, comp, cons, func, inst, pack, ret, sig, sub, var. - HEADER INSERTION (`C-c C-t h'): A customized header can be inserted including the actual file name, user name, and current date as well as prompted title strings. A custom header can be defined in a separate file (see custom variable `vhdl-header-file'). - STUTTERING (double strike): Double striking of some keys inserts cumbersome VHDL syntax elements. Stuttering can be disabled by variable `vhdl-stutter-mode' and be toggled by typing `C-c C-s'. '' --> " [ --> ( ---> comment ;; --> " : " [[ --> [ --CR --> comment-out code ;;; --> " := " ] --> ) ----> horizontal line .. --> " => " ]] --> ] ---- --> display comment ,, --> " <= " aa --> A zz --> Z - WORD COMPLETION (`TAB'): Typing `TAB' after a (not completed) word looks for a word in the buffer that starts alike and inserts it. Re-typing `TAB' toggles through alternative word completions. This also works in the minibuffer (i.e. in template generator prompts). Typing `TAB' after a non-word character indents the line if at the beginning of a line (i.e. no preceding non-blank characters), and inserts a tabulator stop otherwise. `M-TAB' always inserts a tabulator stop. - COMMENTS (`--', `---', `----', `--CR'): `--' puts a single comment. `---' draws a horizontal line for separating code segments. `----' inserts a display comment, i.e. two horizontal lines with a comment in between. `--CR' comments out code on that line. Re-hitting CR comments out following lines. `C-c C-c' comments out a region if not commented out, uncomments out a region if already commented out. You are prompted for comments after object definitions (i.e. signals, variables, constants, ports) and after subprogram and process specifications if variable `vhdl-prompt-for-comments' is non-nil. Comments are automatically inserted as additional labels (e.g. after begin statements) and help comments if `vhdl-self-insert-comments' is non-nil. Inline comments (i.e. comments after a piece of code on the same line) are indented at least to `vhdl-comment-column'. Comments go at maximum to `vhdl-end-comment-column'. `RET' after a space in a comment will open a new comment line. Typing beyond `vhdl-end-comment-column' in a comment automatically opens a new comment line. `M-q' re-fills multi-line comments. - INDENTATION: `TAB' indents a line if at the beginning of the line. The amount of indentation is specified by variable `vhdl-basic-offset'. `C-c TAB' always indents the current line (is bound to `TAB' if variable `vhdl-intelligent-tab' is nil). Indentation can be done for an entire region (`M-C-\') or buffer (menu). Argument and port lists are indented normally (nil) or relative to the opening parenthesis (non-nil) according to variable `vhdl-argument-list-indent'. If variable `vhdl-indent-tabs-mode' is nil, spaces are used instead of tabs. `M-x tabify' and `M-x untabify' allow to convert spaces to tabs and vice versa. - ALIGNMENT: `C-c C-a' aligns port maps, signal and variable assignments, inline comments, some keywords, etc., on consecutive lines relative to each other within a defined region. `C-c M-C-a' only aligns inline comments (i.e. comments that are at the end of a line of code). Some templates are automatically aligned after generation if custom variable `vhdl-auto-align' is non-nil. - KEY BINDINGS: Key bindings (`C-c ...') exist for most commands (see in menu). - VHDL MENU: All commands can be called from the VHDL menu. - INDEX MENU: For each VHDL source file, an index of the contained entities, architectures, packages, procedures, processes, etc., is created as a menu. Selecting a meny entry causes the cursor to jump to the corresponding position in the file. Controlled by variable `vhdl-index-menu'. - SOURCE FILE MENU: A menu containing all VHDL source files in the directory of the current file is generated. Selecting a menu entry loads the file. Controlled by variable `vhdl-source-file-menu'. - SOURCE FILE COMPILATION: The syntax of the current buffer can be analyzed by calling a VHDL compiler (menu, `C-c C-k'). The compiler to be used is defined by variable `vhdl-compiler'. Currently supported are `cadence', `ikos', `quickhdl', `synopsys', `vantage', `viewlogic', and `v-system'. Not all compilers are tested. Please contact me for incorporating additional VHDL compilers. An entire hierarchy of source files can be compiled by the `make' command (menu, `C-c M-C-k'). This only works if an appropriate `Makefile' exists. Compiler options can be defined by variable `vhdl-compiler-options'. - KEYWORD CASE: Lower and upper case for keywords, predefined types, predefined attributes, and predefined enumeration values is supported. If the variable `vhdl-upper-case-keywords' is set to non-nil, keywords can be typed in lower case and are converted into upper case automatically (not for types, attributes, and enumeration values). The case of keywords, types, attributes, and enumeration values can be fixed for an entire region (menu) or buffer (`C-c C-u') according to the variables `vhdl-upper-case-{keywords,types,attributes,enum-values}'. - HIGHLIGHTING (fontification): Keywords, predefined types, predefined attributes, and predefined enumeration values (controlled by variable `vhdl-highlight-keywords'), as well as comments, strings, and template prompts are highlighted using different colors. Unit and subprogram names as well as labels are highlighted if variable `vhdl-highlight-names' is non-nil. The default colors from `font-lock.el' are used if variable `vhdl-customize-colors' is nil. Otherwise, an optimized set of colors is taken, which uses bright colors for signals and muted colors for everything else. Variable `vhdl-customize-faces' does the same on monochrome monitors. Signal highlighting allows distinction between clock, reset, status/control, data, and test signals according to some signal naming convention. Their syntax is defined by variables `vhdl-{clock,reset,control,data,test}-signal-syntax'. Signal coloring is controlled by the variable `vhdl-highlight-signals'. The default signal naming convention is as follows: Signal C R I attributes: clock asynchronous reset synchronous reset S D T control and status data and address test Syntax: signal name ::= "[A-Z][a-zA-Z0-9]*x[CRISDT][a-zA-Z0-9]*" signal identifier -^^^^^^^^^^^^^^^^^ delimiter --------------------------^ above signal attributes -------------^^^^^^^^ additional attributes -----------------------^^^^^^^^^^^^ (`x' is used as delimiter because `_' is reserved by the VITAL standard.) Examples: ClkxCfast, ResetxRB, ClearxI, SelectDataxS, DataxD, ScanEnablexT. If all VHDL words are written in lower case (i.e. variables `vhdl-upper-case-{keywords,types,attributes,enum-values}' are set to nil), make highlighting case sensitive by setting variable `vhdl-highlight-case-sensitive' to non-nil. This way, only names fulfilling the above signal syntax including case are highlighted. - HIDE/SHOW: The code of entire VHDL processes or blocks can be hidden using the `Hide/Show' menu or by pressing `S-mouse-2' within the code (not in XEmacs). - PRINTING: Postscript printing with different fonts (`ps-print-color-p' is nil, default faces from `font-lock.el' used if `vhdl-customize-faces' is nil) or colors (`ps-print-color-p' is non-nil) is possible using the standard Emacs postscript printing commands. Variable `vhdl-print-two-column' defines appropriate default settings for nice landscape two-column printing. The paper format can be set by variable `ps-paper-type'. - CUSTOMIZATION: All variables can easily be customized using the `Customize' menu entry. For some variables, customization only takes effect after re-starting Emacs. Customization can also be done globally (i.e. site-wide, read INSTALL file). Variables of VHDL Mode must NOT be set using the `vhdl-mode-hook' in the .emacs file anymore (delete them if they still are). Maintenance: -----------To submit a bug report, enter `C-c C-b' within VHDL Mode. Add a description of the problem and include a reproducible test case. Questions and enhancement requests can be sent to . The `vhdl-mode-announce' mailing list informs about new VHDL Mode releases. The `vhdl-mode-victims' mailing list informs about new VHDL Mode beta releases. You are kindly invited to participate in beta testing. Subscribe to above mailing lists by sending an email to . The archive with the latest version is located at . Bugs and Limitations: --------------------- Index menu does not work under XEmacs (limitation of XEmacs ?!). - Re-indenting large regions or expressions can be slow. - Hideshow does not work under XEmacs. - Parsing compilation error messages for Ikos and Vantage VHDL compilers does not work under XEmacs. Key bindings: ------------key --z y x w v u t s r q p o n m l binding ------vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps k j i h g f e d c b a , . ] [ ; ' SPC TAB RET DEL ESC C-c vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-caps vhdl-stutter-mode-comma vhdl-stutter-mode-period vhdl-stutter-mode-close-bracket vhdl-stutter-mode-open-bracket vhdl-stutter-mode-semicolon vhdl-stutter-mode-quote vhdl-stutter-mode-dash vhdl-outer-space vhdl-tab vhdl-return backward-delete-char-untabify Prefix Command Prefix Command ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC TAB C-q C-h C-e C-a C-u C-b C-f e a tab-to-tab-stop vhdl-indent-sexp vhdl-mark-defun vhdl-end-of-defun vhdl-beginning-of-defun vhdl-backward-up-list vhdl-backward-sexp vhdl-forward-sexp vhdl-end-of-statement vhdl-beginning-of-statement C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-k C-b C-v C-h C-d C-g C-o C-c ESC C-a TAB C-r C-x C-f C-u C-s C-e C-t vhdl-compile vhdl-submit-bug-report vhdl-version vhdl-help vhdl-kill-line goto-line vhdl-open-line vhdl-inline-comment vhdl-comment-uncomment-region Prefix Command vhdl-align-noindent-region vhdl-indent-line vhdl-regress-line vhdl-show-syntactic-information font-lock-fontify-buffer vhdl-fix-case-buffer vhdl-stutter-mode vhdl-electric-mode Prefix Command C-c ESC C-k vhdl-make C-c ESC C-c ESC C-a vhdl-display-comment-line vhdl-align-comment-region C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t K w W v u t S s r R P p ( k n M m l L i h G g F f x e E d C I c b A a ESC Prefix Command vhdl-while-loop vhdl-wait vhdl-variable vhdl-use vhdl-type vhdl-subtype vhdl-signal vhdl-return-value vhdl-record vhdl-process vhdl-procedure vhdl-paired-parens vhdl-package vhdl-next vhdl-map vhdl-modify vhdl-loop vhdl-library vhdl-if vhdl-header vhdl-generic vhdl-generate vhdl-function vhdl-for vhdl-exit vhdl-entity vhdl-elsif vhdl-disconnect vhdl-constant vhdl-component-instance vhdl-case vhdl-block vhdl-array vhdl-architecture Prefix Command C-c C-c C-c C-c C-t C-t C-t C-t K K K K vhdl-package-textio vhdl-package-std-logic-1164 vhdl-package-numeric-std vhdl-package-numeric-bit C-c C-c C-c C-c C-c C-c C-c C-c C-c C-c C-t C-t C-t C-t C-t C-t C-t C-t C-t C-t ESC ESC ESC ESC ESC ESC ESC ESC ESC ESC t s n b W w S p e C s c a A C-c C-t M-C s vhdl-clocked-wait vhdl-with vhdl-selected-signal-assignment vhdl-port vhdl-else Prefix Command vhdl-concurrent-signal-assignment vhdl-component vhdl-assert vhdl-alias vhdl-configuration-spec C-c C-t M-C d C-c C-t M-C c C-c C-t M-C b vhdl-configuration-decl vhdl-component-configuration vhdl-block-configuration