6.374 Analysis and Design of Digital Integrated Circuits: Problem Set # 2 Solutions

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science 6.374: Analysis and Design of Digital Integrated Circuits Problem Set # 2 Solutions Fall 2003 Issued: 9/18/03 Due: 9/30/03 For these problems you should use the parameters for the 0.25 technology (given in the text) unless otherwise specified for a particular problem. Problem 1: Subthreshold Inverter Operation In circuit applications where extremely low power consumption is essential and high speed operation is not required, subthreshold logic may provide an ideal solution. This problem will explore how far the supply voltage may be lowered before a CMOS inverter fails. For the entire problem, assume that the both devices are minimum length and that the NMOS device has a width of 0.44 um. Failure is defined as the point where an input swing of 0 to VDD produces an output swing less than 10% to 90% of VDD. For this problem use the 0.18 micron technology file which is located in “/mit/6.374/models/log018_1.l”. (Research by Alice Wang) a) Consider the case where the input to the inverter is 0 V. Will the output voltage remain equal to the supply voltage as the supply voltage is lowered to arbitrarily low values? If not, explain what will happen and why. Would using a wider PMOS device increase or decrease the minimum possible supply voltage? Which process corner (TT, FF, SS, SF, or FS) will be the worst case and why? (Variable process conditions may result in a case where the NMOS and PMOS devices have modified mobilities. TT is the case where both devices are typical, SF has slow NMOS and fast PMOS, etc...) Solution When the input is 0 V, Vgs for the NMOS device is 0V and Vgs for the PMOS is -VDD. For typical supply voltages, the current through the PMOS in this case dominates and the output is pulled to VDD. As VDD falls to lower voltages, eventually pushing the PMOS into subthreshold the currents will eventually begin to approach comparable levels and the simple CMOS inverter will become a ratioed circuit. Using a wider PMOS would decrease the minimum possible supply voltage since this would increase the strength of the PMOS relative to the NMOS and allow the PMOS current to overpower the NMOS for lower supply voltages. FS would be the worst case process corner, since the PMOS is weakened in comparison to the NMOS and looses some ability to pull up the output node. So, for a given supply voltage there is a minimum width requirement on the PMOS to maintain proper operation and the minimum size is largest for the FS corner. b) Consider the case where the input to the inverter is VDD. Would using a wider PMOS increase or decrease the minimum supply voltage in this case? Which process corner will be the worst case and why? Solution In this case, Vgs for the PMOS is 0 V and Vgs for the NMOS is lowered with supply voltage. Using a wider 1 PMOS would increase the minimum supply voltage since the PMOS would be stronger and have more leakage current to pull the output up from its desired value of 0 V. The worst case corner would be SF since this would also increase the output voltage for a given supply voltage. So for a given supply voltage, there is a maximum width for the PMOS to maintain proper operation and the maximum width is smallest for the SF corner. Comparing the results for parts a and b, it is clear that since one case requires large PMOS and one case requires small PMOS there must be an optimum PMOS size to operate at the lowest possible supply voltage. c) Now, use HSPICE to simulate the inverter and find the lowest possible supply voltage. Complete one simulation for each input value using the process corners you chose in parts a and b. Use a .DATA statement to vary the width of the PMOS device across the set {0.5u, 1u, 1.5u, 2u, 4u, 8u, 10u, 15u, 30u, 45u, 60u} and sweep VDD from 100mV to 400 mV. Then, using the expressions function in AWaves, plot the ratio of V(out)/VDD. The points where the ratio crosses 0.1 and 0.9 are the failure points. Create a table with three columns containing: PMOS width, minimum supply voltage for the case where the input voltage equals 0, and minimum supply voltage for the case where the input voltage equals VDD. PMOS Width 0.5u 1.0u 1.5u 2u 4u 8u 10u 15u 30u 45u 60u Min. VDD (Vin=VDD 118m 120m 134m 150m 184m 213m 221m 235m 260m 274m 284m Min. VDD (Vin=0) 275m 273m 256m 238m 201m 172m 163m 150m 128m 115m 107m d) Now use your favorite graphing program (Matlab, Excel, etc....) to create a graphical representation for the functional region of operation. On a single graph, plot both cases of (minimum supply voltage, PMOS width) and indicate the region where both conditions are met. What is the lowest possible supply voltage that meets both conditions? What must the PMOS width be to operate at this supply voltage? The mimimum supply voltage is about 190 mV and the PMOS must be about 5 um. 60 50 Min. PMOS W Vin=0/Corner=FS Max. PMOS W Vin=VDD Corner=SF 40 PMOS W (um) 30 20 10 0 100 120 140 160 180 200 220 Supply Voltage (mV) 2 Operational Region Minimum VDD VDD=190 mV W=5um 240 260 280 300 Problem 2: CMOS Logic Consider the following CMOS logic circuits: VDD E VDD 6 A A 6 B 6 C 6 D 6 B E 4 A 4 B 4 B 4 C 4 C 4 D 4 D 4 1 Circuit A 6 6 F A E 6 D 6 F a) 6 C E Circuit B 1 Figure 0.1: Two static CMOS gates. Do the two circuits in Figure 0.1 implement the same logic function? If yes, what is that logic function? If no, give Boolean expressions for both circuits. Solution Yes, they implement the same logic function : F = (ABCD + E) = (A + B + C + D).E b) Assuming we can ignore all second order effects, do these two circuits have the same output resistances when driven with the same input patterns? Solution Yes, they do. The pull down networks are identical and the pull up network can be found by inspection to have the same resistances given the same input pattern. c) Assume the transistors have been sized to give a worst case output resistance of 13 kΩ for the worstcase input pattern. What input patterns (A–E) give the lowest output resistance when the output is low? What is the value of that resistance? Solution The lowest output resistance is obtained when all inputs (A, B, C, D and E) are equal to 1. In that case, the output resistance is the parallel of the resistance of a NMOS of width 1, with a series of four equal nMOS of width 4. Both combinations have the same resistance, equal to the worst-case output resistance, 13 k Ω . Then the output resistance, in this case, is half this value, 6.5 k Ω . d) What input patterns (A–E) give the lowest output resistance when the output is high? What is the value of that resistance? 3 Solution The lowest output resistance is obtained when all inputs are equal to zero. Each of the PMOS have the same width, so all of them have the same resistance. The worst case resistance happens when only one of the inputs (A, B, C or D) is equal to 0 while all the rest are equal to 1. The output resistance in that case is the series of the resistance of two of the PMOS and it is equal to 13 k Ω . Then, each of the pMOS has an output resistance equal to 6.5 k Ω . The output resistance is equal to the series of one of these resistance with the parallel of four of the same resistnaces. Then, the minimum output resistance is 6.5 k Ω + 6.5 k Ω /4 = 8.125 k Ω . e) Neglecting parasitics and assuming a load capacitance of 100 fF, find the best case and worst case tplh and tphl. Solution We can use the RC time constant method of t=0.69*Req*CL . For the worst case, R=13 K for both pull-up and pull-down and the tplh and tphl are both equal to 0.9 ns. For the best case tphl we know that R=6.5 K so tphl=0.45 ns. For the best case tplh we know that R=8.125 K so tplh=0.56 ns. f) Now consider a few second order effects on the propagation delays. Which circuit is optimized for the case when it is known a priori that E will be the last input to arrive and why? How will body effect influence the performance of Circut A vs. Circut B? Solution Circuit B is optimized for the case when ‘E’ will arrive last. The only difference between the two circuits is the pull up network. The nodes between (ABCD) and (E) can use the time before E arrives to charge up to VDD therefore reducing the time required for the overal circuit to charge after E does arrive. Circuit B is also preferable due to the lower influence of body effect. All four parallel devices in Circuit A may experience an increase in threshold voltage and consequent decrease in drive strength due to body effect. g) For parts g and h, consider only Circuit B. Each intermediate node has some parasitic capacitance that must be charged and discharged at each transition. Therefore, the propagation delay is a function of both the initial voltage conditions on the internal nodes and the inputs. The inital voltage conditions, however, are determined by the previous inputs. Which set of previous and current inputs will cause the slowest tplh? Which will cause the slowest tphl? Solution For the worst case low-to-high output transition, all internal caps should initially be discharged to ground which gives a worst case previous input of[ABCDE]=[11110]. Then, the following input should leave all of those capacitances exposed to the output node so [ABCDE]=[11100]. For the high-to-low transition, we should have [ABCDE]=[11100] as the previous input to charge up the internal nodes, then [ABCDE]=[11110] to discharge through a single path only. h) Let all devices be minimum length and set the widths according to the relative scale in the diagram with 1=0.375 um, specify your source and drain areas and perimiters, and include an additional 10 fF load. Use Nanosim to verify functionality by creating an input file which tests the following set of inputs [ABCDE]=[00000, 00001, 11110, 11100, 11111]. Verify that your simulated output values match the expected logic function. Submit your Nanosim output file. Solution 4 Your output file should show that, for the input list above, the output should be [OUT]=[1, 0, 0, 1, 0] Problem 3: Pseudo-NMOS Logic Consider the circuit of Figure 0.2. a) What is the output voltage if only one input is high? If all four inputs are high? Solution 2  V min  W  I D = k′ ⋅ ----- ⋅ V GT ⋅ V min – ----------------- ⋅ ( 1 + λ ⋅ V DS ) L  2    Consider a case when one input is high: A = VDD and B = C = D = 0 V. Assume that Vout is small enough that Vmin = VDSAT for the PMOS device, and Vmin = VDS = Vout for the NMOS devices. Solve for Vout by setting the drain currents in the PMOS and NMOS equal to each other, |IDP| = |IDN|, where the drain currents are functions of Vout, VDD, and the device parameters. Vout = 102 mV, and ID = 35.7 µA. Now verify that the assumptions for Vmin are correct. For the PMOS: VDS = -2.34 V, VDSAT = -1 V, VGT = 2.1 V, therefore Vmin = VDSAT. For the NMOS: VDS = 102mV, VDSAT = 630mV, VGT = 2.07 V, therefore Vmin = VDS. Consider the case when all inputs are high: A = B = C = D = VDD. For these hand calculations, this is numerically equivalent to a circuit with a single NMOS device with W/L = 4*1.5 and its gate tied to VDD. Now, the analysis used above for the case when one device is on can be reused, replacing W/L of the NMOS with 6, and using the same assumptions for Vmin. Vout = 25 mV, and ID = 35.9 µA. The assumptions for Vmin are correct. b) What is the average static power consumption if, at any time, each input turns on with an (independent) probability of 0.5? 0.1? Solution Notice in part a) that the drain current in the PMOS is 35.7 µA with one NMOS on and 35.9 µA with four NMOS devices on. The current in the PMOS can be approximated as 35.8 µA when any number of NMOS devices are on and 0 µA when all four are off. The probability that all four NMOS devices are off is (1−ρ)4 where ρ is the probability an input is high. Therefore, 4 4 P AVG = P OFF ⋅ ( 1 – ρ ) + P ON ⋅ [ 1 – ( 1 – ρ ) ] where POFF = 0 W, and PON = 89.5 µW. PAVG = 83.9 µW when ρ = 0.5 and PAVG = 30.7 µW when ρ = 0.5. c) Compare your analytically obtained results to a SPICE simulation. Solution From SPICE: Vout = 98.7 mV, and ID = 38.2 µA with one NMOS device on and Vout = 23.5 mV, and ID = 5 38.3 µA with all NMOS devices on VDD (W/L) = 0.6 F A B C D (W/L) = 1.5 Figure 0.2 Pseudo-NMOS gate. Problem 4: Pass Transistor Logic and Level Restoration Consider the circuit of Figure 0.3. Assume the inverter switches ideally at VDD/2, neglect body effect, channel length modulation and all parasitic capacitance throughout this problem. Pass Transistor Network VDD VDD = 2.5V B M2 Mn1 A B x Out M1 Mn2 (W/L)2 = 1.5um/0.25um (W/L)1 = 0.5um/0.25um (W/L)ni = 0.5um/0.25um kn’ = 115uA/V2, kp’ = -30uA/V2 VtN = 0.43V, VtP = -0.4V Figure 0.3 Level restoring circuit. a) What is the logic function performed by this circuit? Solution The circuit is a NAND gate. b) Explain why this circuit has non-zero static dissipation. Solution When A=B= VDD, the voltage at node x is VX=VDD-VtN. This causes static power dissipation at the inverter the pass transistor network is driving. c) Using only just 1 transistor, design a fix so that there will not be any static power dissipation. Explain how you chose the size of the transistor. Solution 6 The modified circuit is shown in the next figure . VDD VDD Mr B M2 A Mn1 x Out M1 B Mn2 The size of Mr should be chosen so that when one of the inputs A or B equals 0, either Mn1 or Mn2, would be able to pull node X to VDD/2 or less. d) Implement the same circuit using transmission gates. Solution The circuit is shown below. B Out A B e) Replace the pass-transistor network in Figure 0.3 with a pass transistor network that computes the following function: x = ABC at the node x. Assume you have the true and complementary versions of the three inputs A,B and C. Solution One possible implementation is shown: 7 B C A C C ABC B B Problem 5: Device Modeling - DIBL The standard equation for modeling subthreshold leakage current given in the notes is Id = Io ⋅ e V GS – V T -----------------------nV th –V DS ------------  V th   ⋅ 1–e     . This equation does not account for higher order effects like DIBL. The following BSIM equation adds the DIBL effect to the model: Id = Io ⋅ e V GS – V To – ( γ' ⋅ V SB ) + η ⋅ V DS -------------------------------------------------------------------------------nV th –V DS ------------  V th   ⋅ 1–e     . Using this new equation, we will produce a model for the subthreshold leakage in the 0.25 µ m process used in 6.374. a) Using HSPICE, plot Id vs VGS for a single NMOS device with VD = VDD = 2.5V and W/L = 0.5um/0.25um. We are only interested in the subthreshold region, so sweep VGS over the appropriate range. Using HSPICE, plot Id vs VDS for VGS=0V over the full range of VDS. Plot the current on a log scale for both plots. You will need to extract the points along these curves to use in your favorite analysis program (ie Matlab) for the rest of this problem. The following statement in HSPICE prints a table of the sweeping value and the current through a MOSFET to the HSPICE output stream: .print dc i(Mn1) 8 SOLUTION: I vs V d −6 GS for NFET I vs V d −11 10 DS for NFET 10 −7 10 −8 I (A) −9 −12 10 d 10 d I (A) 10 −10 10 −11 10 −12 10 −13 0 0.05 0.1 0.15 0.2 0.25 VGS (V) 0.3 0.35 0.4 0.45 10 0 0.5 1 1.5 2 2.5 VDS (V); VGS=0 Plots of simulated subthreshold current vs VGS and vs VDS. b) Using the data from the Io vs VGS plot, extract a value for S, the subthreshold slope, in mV/decade. Plot S as it varies with VGS. Over which range of VGS is S likely to be the most accurate for modeling? Plot “instantaneous n” as it varies with S. Over which range is it likely to be accurate for modeling? SOLUTION: The slope of the curve in the Id vs VGS plot is 1/S. To find S, we need to find the slope of the curve and then take its inverse. We cannot calculate the derivative directly because we want S to be in units of mV/decade. Thus we take the log of the current before finding the slope (notice that we can plot the log10(Id) vs VGS on a linear scale and get the same shape curve as in the simulation plot above). The following expression then gives the subthreshold slope in mV/decade: ∆V S = ---------------------- . In Matlab, this might look like: S = delV./diff(log10(Id)); ∆ log ( I d ) where delV is the voltage step in mV. We can solve for “instantaneous n” using S=nVthln(10). The plots for S and “instantaneous” n appear on the following page. The region of interest is clearly the right side of the graph (VGS about 0.15V and above). The rise in S at low voltages comes from the tail-up of current. This increase in current at low VGS and high VDS results from the GIDL effect (Gate Induced Diode Leakage). For modeling purposes, we will select a value of S and n from the regions of the plots where the slope is more constant. 9 S vs VGS "instantaneous" n vs VGS 240 4 220 3.5 200 3 "instantaneous" n S (mV/decade) 180 160 140 120 2.5 2 100 1.5 80 60 0 0.05 0.1 0.15 0.2 0.25 VGS (V) Plot of S vs VGS. 0.3 0.35 0.4 0.45 1 0 0.05 0.1 0.15 0.2 0.25 VGS (V) 0.3 0.35 0.4 0.45 Plot of “instantaneous n” vs VGS. c) Now we will construct a model for the subthreshold behavior of the FET using the BSIM equation. This model should accurately represent the behavior of the FET that you saw in part a). The BSIM equation still is a reasonably low order model, so do not expect your final result to match the plots precisely - just try for a ballpark match. To develop the model, you need to select three parameters: n, Io, and η . The value for n should be somewhere in the range that you plotted in b). Select Io so that the drain current supplied by the model matches the simulated value at VGS=VT0. Hints: Pick an initial value for η and use it with your estimates for n and Io in the model equation for varying VDS. η controls the slope of the curve versus VDS. Once the slopes are roughly equivalent, use your estimate of η to find the current while sweeping VGS. Select values of n and Io that give a good fit. Now use those values in the other case to refine your choice of η . Iterate this process a few times until you are satisfied with the models. It is helpful to convince yourself (by experimentation or from the equation) of the effects of the different parameters on the current. Remember, there is a range of “right” answers to this part of the problem. Also, be glad you don’t do this for a living :) Turn in a plot of Io vs VGS with the real data and the model data on the same plot. Do the same for Io vs VDS. What were your values for Io, n, and η ? Comment briefly on what you consider to be a “good” fit using this model for this process (ie - is it more important to get the slope right or the actual values? is it better to overestimate or underestimate the current? etc). Why is your model a good choice? We selected n = 1.55, η = 0.019, and Io = 1.0715E-7A. The choice of Io causes the subthreshold current to match the simulated value at VGS=VT0 for our choice of η and n. We selected n such that the difference between the model and the simulation was very small at VGS=0. This allows our model for varying VDS to match more closely in magnitude. This approach may not be ideal, however. By matching the magnitude of the current at VGS=0, we actually do a fairly poor job of matching the slope of the curve vs VGS. If matching the magnitude of the curve vs VDS is not so important, we could do a better job of matching the slope vs VGS. Also, the choice of η changes the slope of the curve as VDS varies. Again, different choices of this parameter allow a better match over different regions of the curve. You see that the limitations of this model force some trade-offs in the decision 10 about the “best match”. Model and I versus V d −6 Model and I versus V GS d −10 10 DS 10 Measured Id Modeled Id Measured Id Modeled Id −7 10 −8 −11 10 Current (A) Current (A) 10 −9 10 −10 −12 10 10 −11 10 −12 10 −13 0 0.05 0.1 0.15 0.2 0.25 VGS (V) 0.3 0.35 0.4 0.45 10 0 0.5 1 1.5 2 2.5 VDS (V) Models and Simulated Data. Problem 6: DCVSL Gate Design a) Implement the function S = ABC + ABC + ABC + ABC using transmission gate logic. What function does this circuit implement. Solution This is the ‘Sum’ bit of a one bit carry-in adder. A pass transistor implementation is shown below. The transmission gate implementation you designed will have a PMOS in parallel with each NMOS driven by the complement of the signal that drives the NMOS. B B C C A A S A A Pass Gate Implementation 11 b) Now, design a DCVSL gate which implements the same function. Assume A, B, C, and their complements are available as inputs. Solution One implementation of this circuit is shown on page 50 of Handout #3. c) Simulate your DCVSL implementation in HSPICE with 30 fF load capacitance on each output. Assume that W/L = 0.5u/0.25u for all NMOS transistors and W/L = 2u/0.25u for all PMOS. Does your circuit work? If not, explain why and resize the PMOS devices to fix the problem. Solution The circuit will not work with this sizing because the PMOS is too large and the NMOS pull-down network will be unable to pull the outputs down to the required value for switching to occur. A more reasonable size for the PMOS is around 0.5 um. d) Assuming W/L = 0.5u/0.25u for all nmos transistors and W/L = WP/0.25u for the pmos transistors (where WP is the value you chose in part c), produce a layout of the gate using Magic. Your layout should conform to the following datapath style: (1) Inputs should enter the layout from the left in polysilicon; (2) The outputs should exit the layout at the right in polysilicon (since the outputs would probably be driving transistor gate inputs of the next cell to the right); (3) Power and ground lines should run vertically in metal 1. Extract and simulate your circuit to verify functionality. Solution One possible layout is shown below: 12