VLSI Design Solutions 5

CHAPTER 9 SOLUTIONS 9.27 NAND3 unfooted φ 1 A 3 B 3 C footed NOR3 Y A gd 3 φ 1 A 4 B 4 C 4 φ 1 1 B 2 = 4/3 B 2 2 4 Y = 1/3 1 φ A 1 C gd Y gd 1 =1 Y C 2 gd = 2/3 9.28 Y_h = A + B + C A_h φ B_h C_h A_l Y_l = A + B + C B_l C_l φ 9.29 φ C_h A_h B_h A_h A_l B_h B_l C_l A_l B_l φ 9.30 Your results should be similar to those of Figure 6.37. 9.31 The worst case is when A is low on one cycle, B, C, and D are high, and all the internal nodes become predischarged to 0. Then D falls low during precharge. Then A goes high during evaluation. The NAND has 11 units of capacitance on Cout precharged to VDD and 7.5 units of internal capacitance (C1, C2, C3) that will be ini- 45 46 SOLUTIONS tially low. The output will thus droop to 11/(11+7.5) VDD = 0.59 VDD. φ 1 A 5 B 5 C 5 D 5 5 Cout C1 C2 C3 5/2 Y 5h + 5 + 1 5/2 5/2 5/2 No effect on charge sharing 9.32 The droop is (6+5h)/(6+5h+7.5). Charge sharing is less serious at high fanout. 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 h 9.33 With a secondary precharge transistor, one of the internal nodes is guaranteed to be high rather than low. Thus 11 + 2.5 = 13.5 units of capcitance are high and 5 units are low, reducing the charge sharing noise to 13.5 / (13.5 + 5) VDD = 0.73 VDD. 9.34 The simulated output droops to 0.85 V = 0.46 VDD, somewhat lower than 0.59 VDD predicted in Exercise 6.31. The capacitance of the internal nodes is larger than anticipated. According to Table 5.5, the diffusion capacitance on an uncontacted (merged) node is 1.41 / 1.67 times that of gate capaictance. Using this figure, the expected droop is 11/(11+3 * 5 * 1.41/1.67) = 0.465, an excellent match with simu- CHAPTER 9 SOLUTIONS lation. Input Output 0.85V *634-631.sp *********************************************************************** * Parameters and models *********************************************************************** .param SUP=1.8 .param P = 4 .param N = 20 .option scale=90n .lib '../models/mosistsmc180/opconditions.lib' TT .option post *********************************************************************** *subcircuit *********************************************************************** .subckt inv In Out N=16 P=32 * Assumes 5 lambda of diffusion on the source/drain m1 Out In Gnd Gnd nmos l=2 w=N as='5*N' ad='5*N' + ps='2*N+10' pd='2*N+10' m2 Out In Vdd Vdd pmos l=2 w=P as='5*P' ad='5*P' + ps='2*P+10' pd='2*P+10' .ends *********************************************************************** * Simulation netlist *********************************************************************** Vdd vdd gnd 'SUPPLY' Vin A gnd PULSE 0 'SUPPLY' 200ps 100ps 100ps 500ps 1000ps Vclk clk gnd PULSE 0 'SUPPLY' 100ps 100ps 100ps 500ps 1000ps .global vdd gnd m1 Y clk Vdd Vdd pmos l=2 W=P as='5*P' ad='5*P' + m2 + m3 Y A h vdd h gnd i gnd nmos l=2 W=N nmos l=2 w=N ps='2*P+10' pd='2*P+10' as='3*N' ad='5*N' ps='2*N+6' pd='2*N+10' as='3*N' ad='0' 47 48 SOLUTIONS + m4 + m5 + m6 + X2 i vdd j gnd nmos l=2 w=N j gnd l gnd nmos l=2 W=N l clk gnd gnd nmos l=2 W=N Y inv Z ps='2*N+6' pd='0' as='3*N' ad='0' ps='2*N+6' pd='0' as='3*N' ad='0' ps='2*N+6' pd='0' as='5*N' ad='0' ps='2*N+10' pd='0' N='N/3' P='2*N/3' *********************************************************************** * Stimulus *********************************************************************** .ic v(y)='SUPPLY' v(h)=0 v(i)=0 v(j)=0 v(l)=0 .trans 1ps 2000ps .end 9.35 H = 500 / 30 = 16.7. Consider a two stage design: footless dynamic OR-OR-ANDINVERT + HI-skew INV. G = 2/3 * 5/6 = 10/18. P = 5/3 + 5/6 = 5/2. F = GBH = 9.3. f = F1/2 = 3.0. D = 2f + P = 8.6 τ. The inverter size is 500 * (5/6) / 3.0 = 137. 15 110 30 30 30 30 27 9.36 One design is: Dynamic NAND2 - HI skew INV - Dynamic NAND2 - HI skew INV. G = 1 * (5/6) * 1 * (5/6) = 25/36. F = (25/36) * 8 * 9.6 = 53.3. P = 4/3 + 5/6 + 4/3 + 5/6 = 4.3. f = F1/4 = 2.7. D = 4f + P = 15.1 τ. A0 φ 5 14 H 2-way branch φ 11 H 4-way branch 30 96 CHAPTER 9 SOLUTIONS 9.37 φ φ 9.38 The static designs with and without complex AAOI gates use 28 and 40 transistors, respectively. The nonrestoring transmission gate design uses 16 transistors, though adding inverters on the inputs would raise that to 24 and make the mux restoring but inverting. Adding an output inverter to make the mux noninverting brings the transistor count to 26. S0 S1 S0 D0 D0 D1 D1 D2 D2 D3 D3 S0 D0 D1 D0 D1 S1 S1 49 SOLUTIONS 9.39 C B B A A C B B B B C A A Y B Y B B C A B B C L B A L Y C C C Y (f) DCVSPG B A C C B A B (h) PPL L Y B A L Y L Y L Y B A B A (g) SRPL BABA B A B (c) dual-rail domino B A B A C C B A B B A B A Y B A C B Y (e) EEPL (d) CPL B A B B H C φ B A Y B A B A φ C B A B A C C C A C B A B A Y B (b) pseudonMOS (a) static CMOS C C A H 50 Y A B A B B C C Y C A Y B A B C C (i) DPL B A C C Y B A B (j) LEAP L Y CHAPTER 9 SOLUTIONS 9.40 Y_l A Y A B B B_h (b) pseudo-nMOS A_l A L Y L Y A (d) CPL B B Y A Y Y L Y B B A A L Y L Y B B A B A L A A B (j) LEAP B Y Y B A B Y B A (g) SRPL (f) DCVSPG (i) DPL L (e) EEPL A A B_l φ B B A B Y_h (c) dual-rail domino B A B H A_h B (a) static CMOS φ H Y Y Y (h) PPL 51 52 SOLUTIONS 9.41 ### no solution available 9.42 When the clock is low, the two outputs equalize at VDD/2. When the clock rises, one side pulls down, fully turning ON the pMOS transistor to pull the other side up. This gate saves precharge power relative to dynamic logic because the precharge equalizes the two outputs rather than drawing power from the rail. The partial swing may lead to faster transitions. However, it consumes extra power early in evaluation because of contention between the partially ON pMOS transistor and the ON pulldown stack. φ Y/Y 9.43 n/a 9.44 The nMOS is in the linear region and the pMOS is saturated. By KCL Chapter 10 10.1 (a) tpd = 500 - (50 + 65) = 385 ps; (b) tpd = 500 - 2(40) = 420 ps; (c) tpd = 500 - 40 = 460 ps. 10.2 (a) tpd = 500 - (50 + 65 + 50) = 335 ps; (b) tpd = 500 - 2(40) = 420 ps; (c) tpd = 500 (50 + 25 - 80 + 50) = 455 ps. 10.3 (a) tcd = 30 - 35 = 0; (b) tcd = 30 - 35 = 0; (c) tcd = 30 - 35 - 60 = 0; (d) tcd = 30 - 35 + 80 = 75 ps. 10.4 (a) tcd = 30 - 35 + 50 = 45 ps; (b) tcd = 30 - 35 + 50 = 45 ps; (c) tcd = 30 - 35 + 50 60 = 0; (d) tcd = 30 - 35 + 80 + 50 =125 ps. 10.5 (a) tborrow = 0; (b) tborrow = 250 - 25 = 225 ps; (c) tborrow = 250 - 25 - 60 = 165 ps; (d) tborrow = 80 - 25 = 55 ps. 10.6 (a) tborrow = 0; (b) tborrow = 250 - 25 - 50 = 175 ps; (c) tborrow = 250 - 25 - 60 -50 = 115 ps; (d) tborrow = 80 - 25 - 50 = 5 ps. 10.7 If the pulse is wide and the data arrives while the pulsed latch is transparent, the CHAPTER 10 SOLUTIONS latch contributes its D-to-Q delay just like a regular transparent latch. If the pulse is narrow, the data will have to setup before the earliest skewed falling edge. This is at time tsetup - tpw + tskew before the latest rising edge of the pulse. After the rising edge, the latch contributes a clk-to-Q delay. Hence, the total sequencing overhead is tpcq + tsetup - tpw + tskew. 10.8 tsetup-flop = tsetup-latch + tnonoverlap; thold-flop = thold - tnonoverlap; tpcq-flop = tpcq. 10.9 (a) 1200 ps: no latches borrow time, no setup violations. 1000 ps: 50 ps borrowed through L1, 130 ps through L2, 80 ps through L3. 800 ps: 150 ps borrowed through L1, 330 ps borrowed through L2, L3 misses setup time. (b) 1200 ps: no latches borrow time, no setup violations. 1000 ps: 100 ps borrowed through L2, 50 ps through L4. 800 ps: 200 ps borrowed through L2, 200 ps borrowed through L3, 350 ps borrowed through L4, 250 ps borrowed through L1, L2 then misses setup time. 10.10 (a) 700 ps; (b) 825 ps; (c) 1200 ps. 10.11 (a) 700 ps; (b) 825 ps; (c) 1200 ps. The transparent latches are skew-tolerant and moderate amounts of skew do not slow the cycle time. 10.12 _s1 Δ2 clk _s2 _s2 Δ3 clk _s1 _s1 Δ4 clk Latch 4 _s1 Latch 3 Flop Δ1 clk Latch 2 _s2 _s2 Latch 1 clk _s2 10.13 The tpdq delays are 151 ps for a conventional dynamic latch and 162 ps for a TSPC latch. *713-latch.sp *********************************************************************** * Parameters and models *********************************************************************** .param SUP=1.8 .option scale=90n .lib '../models/mosistsmc180/opconditions.lib' TT .option post *********************************************************************** * Subcircuits *********************************************************************** .global vdd gnd .subckt inv In Out N=4 P=8 * Assumes 5 lambda of diffusion on the source/drain m1 Out In Gnd Gnd nmos l=2 w=N as='5*N' ad='5*N' 53 54 SOLUTIONS + m2 + Out In Vdd Vdd pmos l=2 w=P ps='2*N+10' pd='2*N+10' as='5*P' ad='5*P' ps='2*P+10' pd='2*P+10' .ends .subckt latchd c nc D Q N=4 P=4 X1 D x inv m1 Q c x gnd nmos l=2 w=N as='5*N' ad='5*N' + ps='2*N+10' pd='2*N+10' m2 Q nc x vdd pmos l=2 w=P as='5*P' ad='5*P' + ps='2*P+10' pd='2*P+10' .ends *********************************************************************** * Simulation netlist *********************************************************************** Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 400ps 100ps 100ps 2000ps 4000ps Vclk clk gnd PULSE 0 'SUPPLY' 200ps 100ps 100ps 1000ps 2000ps Vnclk nclk gnd PULSE 'SUPPLY' 0 200ps 100ps 100ps 1000ps 2000ps X1 clk nclk a D latchd X2 clk nclk D Q latchd M=4 X3 clk nclk Q Y latchd M=16 *********************************************************************** * Stimulus *********************************************************************** .trans 1ps 4000ps .measure tdqf + TRIG v(D) VAL='SUPPLY/2' RISE=1 + TARG v(Q) VAL='SUPPLY/2' FALL=1 .measure tdqr + TRIG v(D) VAL='SUPPLY/2' FALL=1 + TARG v(Q) VAL='SUPPLY/2' RISE=1 .measure tdq param='(tdqf+tdqr)/2' .end *713-tspc.sp *********************************************************************** * Parameters and models *********************************************************************** .param SUP=1.8 .option scale=90n .lib '../models/mosistsmc180/opconditions.lib' TT .option post *********************************************************************** * Subcircuits *********************************************************************** .global vdd gnd CHAPTER 10 SOLUTIONS .subckt tspclatch c D Q N=4 P=8 m1 + m2 + m3 + x D vdd vdd pmos x c y gnd nmos y D gnd gnd nmos l=2 w=P as='5*P' ad='5*P' ps='2*P+10' pd='2*P+10' l=2 w=N as='5*N' ad='5*N' ps='2*N+10' pd='2*N+10' l=2 w=N as='5*N' ad='5*N' ps='2*N+10' pd='2*N+10' m4 Q x vdd vdd pmos l=2 w=P as='5*P' ad='5*P' + ps='2*P+10' pd='2*P+10' m5 Q c z gnd nmos l=2 w=N as='5*N' ad='5*N' + ps='2*N+10' pd='2*N+10' m6 z x gnd gnd nmos l=2 w=N as='5*N' ad='5*N' + ps='2*N+10' pd='2*N+10' .ends *********************************************************************** * Simulation netlist *********************************************************************** Vdd vdd gnd 'SUPPLY' Vin A gnd PULSE 0 'SUPPLY' 400ps 100ps 100ps 2000ps 4000ps Vclk clk gnd PULSE 0 'SUPPLY' 200ps 100ps 100ps 1000ps 2000ps X1 clk A D tspclatch X2 clk D Q tspclatch m=4 X3 clk Q Y tspclatch M=16 *********************************************************************** * Stimulus *********************************************************************** .trans 1ps 4000ps .measure tdqf + TRIG v(D) VAL='SUPPLY/2' + TARG v(Q) VAL='SUPPLY/2' .measure tdqr + TRIG v(D) VAL='SUPPLY/2' + TARG v(Q) VAL='SUPPLY/2' .measure tdq param='(tdqf+tdqr)/2' .end RISE=1 RISE=1 FALL=1 FALL=1 55