MIPS Registers - Assembly Instructions

MIPS registers register assembly name Comment r0 $zero Always 0 r1 $at Reserved for assembler r2-r3 $v0-$v1 Stores results r4-r7 $a0-$a3 Stores arguments r8-r15 $t0-$t7 Temporaries, not saved r16-r23 $s0-$s7 Contents saved for later use r24-r25 $t8-$t9 More temporaries, not saved r26-r27 $k0-$k1 Reserved by operating system r28 $gp Global pointer r29 $sp Stack pointer r30 $fp Frame pointer r31 $ra Return address MIPS insruction formats Instruction ÒaddÓ belongs to the R-type format. opcode rs rt rd 6 5 5 5 src src dst add $s1, $s2, $t0 shift amt function 5 6 will be coded as 0 18 8 17 6 5 5 5 0 32 5 6 The ÒfunctionÓ field is an extension of the opcode, and they together determine the operation. Note that ÒsubÓ has a similar format. Instruction ÒlwÓ (load word) belongs to I-type format. opcode rs rt 6 5 5 16 base dst offset lw $t0, 32($s3) address will be coded as 35 19 8 6 5 5 32 16 Both ÒlwÓ and ÒswÓ (store word) belong to I-format. MIPS has (fortunately) only three different instruction formats. The operation codes determine the format. This is how the control unit interprets the instructions. MEMORY 0 4 8 12 16 20 24 28 32 REGISTERS 0 r0 r1 r2 r3 destination r8 ($t0) Offset r17 ($s1) r18 ($s2) + r19 ($s3) base Effective address (LW) LoadWord destination, offset($base register) What is an Assembler? A simple piece of software Assembly Language Assembler Machine Language lw t0, 32($s3) Binary code: add $s1, $s2, $t0 Consists of 0Õs and 1Õs only If you know the instruction formats, then you can translate it. The machine language consists of 0Õs and 1Õs Pseudo-instructions (Makes your life a bit simpler) These are simple assembly language instructions that do not have a direct machine language equivalent. During assembly, the assembler translates each pseudoinstruction into one or more machine language instructions. Example move $t0, $t1 # $t0 ← $t1 The assembler will translate it to add $t0, $zer0, $t1 We will see more of these soon. Think about these Q1. How will you load a constant into a memory location (i.e. consider implementing x :=3)? (Need some immediate mode instructions, like li which is a pseudo-instruction) Q2. How will you implement x:= x+1 in assembly language? What do you think? Q3. Why is the load (and store too) instruction so Òcrooked?Ó Used for its flexibility, let us discuss it. Q4. How will you load a constant (say 5) into a register? (Need the immediate mode instructions, like addi) Loading a 32-bit constant into a register The pseudo-instruction Òload immediateÓ li $s0, 0x 003A0012 hexadecimal means Òload the 32-bit constant into register $s0.Ó Internally it is translated into lui $s0, 42 # load upper-half immediate ori $s0, $s0, 18 # (one can also use andi) Logical Operations Shift left (logical) sll Shift right (logical) srl Bit-by-bit AND and, andi (and immediate) opcode rs rt rd 6 5 5 5 src src dst shift amt function 5 6 sll $t2, $s0, 4 means $t2 = $s0 << 4 bit position (s0 = $16, t2 = $10) 0 6 0 16 10 5 5 5 4 5 0 6 s0 = 0000 0000 0000 0000 0000 0000 0000 1001 t2 = 0000 0000 0000 0000 0000 0000 1001 0000 Why are these instructions useful? Using AND for bit manipulation To check if a register $s0 contains an odd number, AND it with a mask that contains all 0Õs except a 1 in the LSB position, and check if the result is zero (we will discuss decision making later) andi $t2, $s0, 1 This uses I-type format (why?): 8 6 16 5 10 5 1 16 andi s0 t2 Now we have to test if $t2 = 1 or 0 Making decisions if (i == j) then f = g + h; else f = g Ð h Use bne = branch-nor-equal, beq = branch-equal, and j = jump Assume that f, g, h, are mapped into $s0, $s1, $s2 i, j are mapped into $s3, $s4 Else: Exit: bne $s3, $s4, Else # goto Else when i≠j add $s0, $s1, $s2 #f=g+h j # goto Exit (something new**) Exit sub $s0, $s1, $s2 #f=gÐh The program counter and control flow Every machine has a program counter (called PC) that points to the next instruction to be executed. 1028 Instruction 1 1032 Instruction 2 1036 Instruction 3 1028 PC Instruction 4 CPU data data MEMORY Ordinarily, PC is incremented by 4 after each instruction is executed. A branch instruction alters the flow of control by modifying the PC. Compiling a while loop while (A[i] == k) i = i + j; Initially $s3, $s4, $s5 contains i, j, k respectively. Let $s6 store the base of the array A. Each element of A is a 32-bit word. Loop: Exit: add $t1, $s3, $s3 # $t1 = 2*i add $t1, $t1, $t1 # $t1 = 4*i add $t1, $t1, $s6 # $t1 contains address of A[i] lw $t0, 0($t1) # $t0 contains $A[i] add $s3, $s3, $s4 #i=i+j bne $t0, $s5, Exit # goto Exit if A[i] ≠ k j Loop # goto Loop Anatomy of a MIPS assembly language program running on the MARS simulator .data L1: .word 0x2345 # some arbitrary value L2: .word 0x3366 # some arbitrary value Res: .space 4 .text .globl main main: lw $t0, L1($0) #load the first value lw $t1, L2($0) # load the second value and $t2, $t0, $t1 # compute bit-by-bit AND or $t3, $t0, $t1 # compute bit-by-bit OR sw $t3, Res($0) # store result in memory li $v0, 10 syscall # code for program end Another example of input-output str1: res: main: .data .asciiz .align 2 .space 4 .text .globl main li $v0, 4 la $a0, str1 syscall "Enter the number:" #move to a word boundary # reserve space to store result # code to print string li $v0, 5 syscall # code to read integer move $t0, $v0 add $t1, $t0, $t0 sw $t1, res($0) # move the value to $t0 # multiply by 2 # store result in memory li $v0, 1 move $a0, $t1 syscall # code to print integer # move value to be printed to $a0 # print to the screen li $v0, 10 syscall # code for program end