Unit V Digital Eletronics

UNIT V DIGITAL ELETRONICS 5.1 Introduction Generally the electronics is divided into two basic areas: analog and digital electronics. The electronics is a newer and greater between performance as compared to analog electronics. The main difference between analog and digital signal can be stated simply as Analog signals are continuously variable between defined values, and digital signals can vary only by distinct discrete steps. 5.2 Analog system and digital system A system which is capable of processing continuous range of values (or) analog signal called as analog system or analog electronics. EX. Analog meters, physical balance etc. System which process discrete values (or) digital signal is called as digital systems or digital electronics. Ex. Digital calculator, Microprocessor, Digital Computer etc. Advantages of Digital systems 1. 2. 3. 4. 5. Digital systems are easy to design. Information storage is easy. High accuracy and precision can be achieved. It is less affected by noise. The circuit can be easily fabricated in integrated circuits. 5.3 LOGIC GATES A logic gate is a circuit that performs a logic function on a number of binary input signals. The signals at the input and output terminals of gates either at HIGH level voltage (or) at a LOW level voltage. A gate will produce one output level whenever any other combination is present at the inputs. The different types of basic gates available are AND, OR and NOT gate. The logic functions are defined by a truth table. This table lists all the possible combinations of the input variables and output variable applied to a gate. Each variable applied to a gate. Each variable can only be either 0 (logic 0 level) or 1 (logic 1 level). The total number of possible combinations of binary inputs to a gate is determined by N = 2n where N is the number of possible combinations n is the number of bits. For two variables : N = 22 = 4 combinations For three variables : N = 23 5.3.1 AND Gate = 8 combinations The AND Gate is composed of two or more inputs and a single output, performs logical multiplication. The standard symbol for the AND gate is shown is fig.5.1. and its truth table is shown in Table 5.1. The logical operation of the AND gate is such that the output is HIGH (i) when all the inputs are HIGH, otherwise it is LOW (0). The AND Gate expression represent the function Y = A.B. Table 5.1 Truth table of AND Gate Input Output A B Y = A.B 0 0 0 0 1 0 1 0 0 1 1 1 Fig. 5.1 Standard logic symbol AND Gate 5.3.2 OR GATE OR gate, which is composed of two or more inputs and a single output, performs logical addition. The standard symbol for the OR gate is shown in Fig.5.2. and its truth table is shown in Table.5.2. The logical operation of the OR gate is such that the output is HIGH (i) when any of the inputs are HIGH, otherwise it is LOW (0). OR Gate expression represent the function Y = A+B. Table 5.2 Truth table of OR Gate Input Output A B Y = A+B 0 0 0 0 1 1 1 0 1 1 1 1 Fig. 5.2 Standard Logic symbol of OR Gate 5.3.3 NOT Gate The inverter (NOT Gate) performs a basic logic function called inversion or complementation. The purpose of the inverter is to change one logic level (HIGH/LOW) to the opposite logic level. In terms of bits, it changes ‘1’ to ‘0’ and vice verse. The standard logic symbols for the inverter shown in Figure5.3. The truth table for the NOT gate is shown in Table5.3. NOT gate expression represent the function Y = A̅. Table 5.3 Truth table of NOT Gate Input Output A Y = Ā 0 1 1 0 Fig. 5.3 Standard logic symbol of NOT Gate 5.3.4 NAND Gate The NAND, which is composed of two (or) more inputs and a single output, is a very popular logic element because it may be used as a universal function. The term NAND is formed by the concatenation NOT-AND and implies an AND function with an inverted output. The standard symbol for the NAND gate is shown in fig.5.4 and its truth table is shown in Table 5.4. The logical operation of the NAND gate is such that the output is LOW (0) only when all the inputs are HIGH(1). NAND gate expression represent the function Y = Ā¯. ¯B̄. Table 5.4 Truth table of NAND Gate Input Output A B Y = Ā¯. ¯B̄ 0 0 1 0 1 1 1 0 1 1 1 0 Fig. 5.4 Standard Logic symbol of NAND Gate 5.3.5 NOR Gate The NOR gate, which is composed of two (or) more inputs and a single outputs, also has a universal property. The term NOR is formed by the concatenation NOT-OR and implies an OR function with an inverted output. The standard symbol for the NOR gate is shown in Fig.5.5. and its truth table is shown in Table.5.5. The logical operation of the NOR is such that the output is HIGH (1) only when all the inputs are LOW (0). NOR gate expression represent the Y= Ā¯+̄¯B̄. Table 5.5 Truth table of NOR Gate Input Output A B Y = Ā¯+̄¯B̄ 0 0 1 0 1 0 1 0 0 1 1 0 Fig. 5.5 Standard logic symbol NOR Gate 5.3.6 Exclusive-OR (XOR) and Exclusive NOR (XNOR) Gates These gates are usually formed from the combination of the other logic gates. However, because of their functional importance, these gates are treated as basic gates with their own unique symbols. The standard symbol and truth tables for the XOR and XNOR gates, shown in Fig 5.6 and Table 5.6 respectively. The Exclusive –OR is an “inequality” function and the output is HIGH(1) when the inputs are not equal to each other. Conversely, the Exclusive NOR IS AN “equality” function and the output is HIGH (1) when the input s are equal to each other. For XOR gate function is expressed as Y = AB̄ + AB̄ = A+ B For ‘XNOR’ gate function is expressed as Y =AB + Ā¯B̄ = A+B (or) A e B (b) (a) Fig. 5.6 Standard logic symbol of :(a) XOR (b) XNOR Table 5.6 truth table for XOR and XNOR Logic gates Input A B Output Y =A B Y= A B 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 5.4 BOOLEAN FUNCTION A binary variable can have two possible states, namely ‘0’ and ‘1’. A Boolean function is an expression formed with binary variables and logical operators, e.g. X = AB+CD+AD. 5.5 BOOLEAN ALGEBRA Boolean algebra is the mathematics for digital systems. The basic rules for Boolean addition and multiplication are presented in table 5.7. Table 5.7 Boolean Addition and Multiplication Additional Rules Multiplication Rules 0+0=0 0.0=0 0+1=1 0.1=0 1+0=1 1.0=0 1+1=1 1.1=1 5.5.1 LAWS OF BOOLEAN ALGEBRA Commutative Laws The commutative law of addition for two variables is algebraically expressed as A+B = B+A The commutative law of multiplication for two variables is expressed as AB =BA Associative laws The associative law of addition of three variables is expressed as A + (B+C) = (A+B) + C The associative law of multiplication of three variables is expressed as A(BC) = (AB)C Distributive law The distributive law of three variables is expressed as A( B+C) = AB + AC This law states that ORing several variables and ANDing the result is equivalent of ANDing the single variable with each of the variables in the grouping, then ORing is the result. 5.5.2 RULES OF BOOLEAN ALGEBRA By combining the laws of Boolean algebra, we form several useful rules that may be used in manipulating and simplifying Boolean algebra expressions. Table 5.8, note that in each case, A, B or C can either represent a single variable of a combination of variables. Table 5.8 Rules of Boolean Algebra Rule Number Boolean Number 1 A+0 =A 2 A+1=1 3 A.0 =0 4 A.1=A 5 A+A =A 6 A+Ā=1 7 A.A=A 8 A. Ā=0 9 "= A A 10 A+AB=A 11 A+B=B+A 12 (A+B)(A+C)=A+BC Among these rules, in particular rules, 1 to 9, are easily verified using truth tables. Let us examine two methods by which we can prove the relationships of rules 10 – 12. First we use the laws and rules of Boolean algebra. Second we employ the use of truth tables. Example 1 Simplify the Boolean function Solution: Method 1: A +A.B = A (1+B) A + AB = A .1 =A Method 2: A B AB A + AB 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1 1 Example 2 Simplify the Boolean Function (A+B) (A+C) Method 1: (A+B) (A+C) = AA + AC + BA + BC = A + AC + BA +BC = A (1+C) +BA + BC = A.1 + BA +BC = A + BA + BC = A (1+B) +BC = A.1 +BC = A +BC Method 2: Table illustrating (A + B) (A+C) = A + BC A B C A+B A+C (A+B)(A+C) BC A+BC 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 5.6 DE MORGAN’S THEOREMS For N variables, DeMorgan’s theorems are expression in the following formulas: Theorem 1 The complement of the product is equivalent to the sum of the complements. ¯ ¯N̄ = A̅ + B̄ + C̅ … N̄ Ā B̄C̄¯ … Theorem 2 The complement of the sum is equivalent to the product of the complements. Ā¯ +̄ ¯B̄ ¯+̄ ¯C̄ +̄¯¯⋯¯+̄ N̄¯ = A̅. B̄. C̅ … N̄ Example 7 Applying Demorgan’s theorem to the expression (¯Ā +̄¯B̄ ¯+̄ ¯C̄)¯D̄ ¯(Ā +̄¯B̄ ¯+̄ ¯C̄)¯D̄ = Ā¯ +̄¯B̄ ¯+̄¯C̄ + D̄ = Ā B̄ C̄ + D̄ Example 3 Applying Demorgan’s theorem to the expression Ā¯B¯C¯ +̄¯D̄ĒF̄ Solution: Ā¯B̄C̄¯ +̄¯D̄ĒF̄ = (ĀB̄¯C̄) (D̄Ē¯F̄) = (Ā + B̄ + C̄)( D̄ + Ē + F̄) 5.7 LOGIC CIRCUITS Recall that the functions associated with logic gates to describe their operation. Accordingly, the interconnected assembly of these gates may be used to create any logic function. The resulting circuit formed by the grouping of these gates is referred to as a logic circuit. The truth tables for logic circuits are constructed by applying each of the possible N = 2n input combinations to the circuit inputs and determining the corresponding output. Figure 5.7 illustrates the logic circuit diagram for the function X = AB+B and the corresponding truth table is listed in table 5.9. Fig. 5.7 Logic circuit for Function X = AB + B Table 5.9 Truth table for Function X = AB + B Input Output A B Y =AB+B 0 0 0 0 1 1 1 0 0 1 1 1 Example 4 Simplify the expression Y = AB + AB . (A+C) Solution : Y Y Y Example 5 = AB + AB . (A + C) = AB + AB . ( A + C) = AB + ABA + ABC = AB (1+A) + ABC = AB (1) + ABC = AB + ABC = AB (1+C) = AB (1+A = 1) Simplify the given logic circuit shown in fig. Ex. 10 (a) and implement the simplified logic circuit using logic gates. Fig. Ex. 5 (a) Solution : From the circuit, the expression for output of logic circuit Y Y = AB + A(B + C) + B (B + C) = AB + AB + AC + BB + BC (A + A = A) = AB + AC + B + BC (B.B =B) = AB + AC + B (1 +C) ((1 + C) =1) = AB + AC + B = B (1 +A) + AC = B + AC Simplified logic circuit Fig. Ex. 5 (b) Example 6 Simplify the expression F = ( A + B) ( A + C) (B + C) Solution : F (or) F = (A + B) (A + C) (B + C) = (AA + AC + BA + BC) (B + C) = (AC + BA + BC) + (B + C) = ABC + BBA + BBC + ACC + BAC + BCC = ABC + BA + BC + AC + BAC + BCC = AC (B + 1) +BA + (A + 1) BC = AC + BA + BC = AC + BA + BC (A + A) = AC + BA + BCA + BCA = AC (1 + B) + BA (1 + C) = AC + BA. 5.8 UNIVERSAL LOGIC GATES The NAND and NOR gates are called universal logic gates because all gates or logic circuits constructed using either NAND or NOR gate. Figure 5.8 shows the equivalency between the basic logic circuits. Similarly, Fig 5.9 shows the equivalency between the basic logic gates and their NOR logic circuits. Fig. 5.8 NAND equivalent circuits Fig. 5.9 NOR Equivalent circuits 5.9 ADDER Adder is a combinational logic circuit, which performs the addition of binary digits. Adder produce two outputs namely sum and carry. Adder circuits can be classified into two types depending on the number of bits in the input variable. 5.9.1 Half Adder Half adder is a logic circuit, which is used to perform two bit binary addition. Figure 5.10(a) shows the block diagram of half adder and the table 5.10 shows the truth table of half adder. Fig. 5.10(a) Block diagram of Half Adder Table 5.10 Truth table of Half adder Input A Output B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Observe from table that we may derive logical expressions for the Sum (S) and carry output (CO) bits. Namely, CO = AB, S= AB, S = A + B. From these two expressions, the implementation of the half adder function is conducted as illustrated in fig 5.10(b). Fig. 5.10 (b) Logic Circuit for Half Adder 5.9.2 Full Adder Full adder is a combinational circuit which performs the arithmetic addition of three input bits. The logical symbol for the full-adder is shown in fig5.11(a) and the associated truth table is table 5.11. Fig. 5.11(a) Block diagram of Full Adder Recall that for the half-adder the sum of A and B is the XOR of those two variables,. Similarly for the three variables A, B and C in the sum becomes. This is illustrated in Fig 5.11(b). Table 5.11 Truth table of Full Adder Inputs Outputs A B Cin C S 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Fig. 5.11 (b) Logic Circuit for the full Adder 5.10 SUBTRACTORS Subtractor is a combinational logic circuit, it performs the subtractor operation. The subtractor will produce a difference and borrow. Subtractor is classified based on the number of bits performed. 1. Half Subtractor and 2. Full Subtractor 5.10.1 Half Subtractor A half subtractor is a combinational logic circuit that performs subtraction involving two bits and produce their outputs as, difference and borrow. The half subtractor needs two inputs : minuend and subtrahend and two output : Borrow and difference fig.5.12(a) shows the block diagram of half subtractor and table 5.12 shows the truth table of half subtractor. Fig. 5.12(a) Block diagram of Full Subtractor Table 5.12 Truth table for Full subtractor Inputs Outputs A B Difference (D) Borrow (B) 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 Logic Diagram The logic diagram is constructed for above expression by using gates, shown in Fig.5.12(b) it is Fig.5.12(b) Logic diagram of Half Subtractor 5.10.2 Full subtractor A full subtractor is a combinational logic circuit that performs subtraction involving three bits, namely minuend bit, subtrahend bit and the borrow from the previous stage. Figure 5.13(a) shows the block diagram of full subtractor and table 5.13 shows the truth table for full subtractor. Fig. 5.13(a) Block diagram of Full Subtractor Table 5.13 Truth table for Full Subtractor Inputs Outputs A B Bin D Bout 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 The full subtractor can be implemented with two half subtractor and one OR gate, as OR in fig. The difference output from the second half subtractor is the exclusive OR of Bin and the first half subtractor, which is same as difference output of full subtractor. 5.11 FLIP FLOPS Flip flops are synchronous bistable storage devices capable of storing one bit. In this case, synchronous means that the output state only changes at a specified point on a triggering input called the clock (C) that is, the output changes are synchronous with the clock signal. 5.11.1 RS flip Flop (Reset- Set Flip Flop) The simplest type of flip flop is the Reset Set (RS) flip flop. It can be condtruced using two NAND gates (or) two NOR gates. Figure 5.14 shows the basic RS flip flop using two NOR gates are cross coupled so that the output of NOR gate 1 is connected to one of the inputs of NOR gate 2 and vice versa. The flip flop has two outputs Q and Q̄,and two inputs, Set and Reset (S and R). the basic operation of flip flop as explained in the four cases as follows Fig. 5.14 Basic Flip Flop using NOR gates Table 5.14 Truth table for RS Flip Flop using NOR Gate R S Q Q̄ State 0 0 NC NC 0 1 1 0 1 0 0 1 1 1 1/0 0/1 No change Set Reset Indeterminate condition Case 1 R = 0 and S =1 In this case, the previous outputs are assumed as Q =1. So the S iput of NOR gate 2 is at logic 1, hence its output, Q̄ is at logic 0. Both inputs to NOR gate 1 are now at logic 0. So that its output, Q is at logic 1. Case 2 R = 1 and S = 0 In this case, R input of NOR gate 1 is at logic 0, hence its output Q is at logic 1 when the previous outputs are considered as Q = 0 and Q̄ = 1. Both inputs of NOR gate 2 is logic 0. So that its output Q̄ is at logic 1. Case 3 R = 0 and S = 0 Let as assume that initially Q= 0 and Q̄ = 1 . With Q̄ = 0 both inputs of NOR gate 1 are at logic 0. So its output Q is at logic 1. With Q =1, one input of NOR gate 2 is at logic 1, hence its output Q̄ is at logic 0. This shows that when S and R both are low, output state does not change. Case 4 R = 1 and S = 0 When R and S both are at logic 1, they force the outputs of both NOR gates to the low gate (Q = 0 and Q̄ = 0). So we call this an indeterminate of prohibited state. This condition also violates the basic definition of a flip flop requires Q̄ to be the complement of Q. Thus in normal operation this condition must be avoided by making sure that 1’s are not applied to the both inputs simultaneously. The truth table of basic flip flop using NOR gates is shown in truth table to simplify the operation. To make synchronization of flip-flop, clock is also applied to the flip flop. This type of flip flop is called clocked flip flop. Fig. 5.15 Clocked RS Flip Flop 5.11.2 Flip Flop using NAND gates The basic flip flop may be constructed using two NAND gates as shown in fig and the truth table of this flip flop as shown in table. In this case S̄ = R̄ = 1 makes the logic levels at the two gate outputs are the same (logic level 1) and hence is not used. Since NAND gates are employed, the inputs exercise control at logic level 0 to maintain the present state. That is, the flop changes state when either input is put to logic 0 or logic 1. Since this situation is inconsistent with the preference discussed earlier, we have labeled the control inputs S̄ and R̄ rather than S and R. To understand how this circuit functions, recall that a low on any input to a NAND gate forces its output high. Thus a low on the S̄ input will be set the flip flop (Q = 1 and Q̄ = 0). A low input of R will be reset it ( Q = 0 and Q̄ = 1 ). If both R̄ and S̄ are high, the flip flop will remain in its previous state. When both R̄ and S̄ inputs are low, the output is unpredictable. Fig. 5.16 RS Flip Flop using NAND Gate 5.11.3 D Flip Flop ( Delay Flip Flop) Looking a the truth table of SR flip flop we can realize that when both inputs are same the output either does not change or it is unpredictable (Inputs – 00, no change and inputs – 11 unpredictable). In many practical applications, these inputs conditions are not required. These input conditions can be avoided by making them complement to each other. This modified clocked SR flip flop is known as D flip flop. As shown in fig, D input goes directly to the S input, and its complement is applied to the R input, through gate 5. Therefore, only two input conditions exist, either S = 0 and R = 1 and S = 1and R = 0. When D = 1, S = 1 and R = 0 and then D =0, S = 0 and R = 1. Therefore, during the occurrence of clock pulse if D =1, the Q output is set and if D = 0, the output is reset. The truth table of clocked D flip flop is shown in Table. Table 5.15 Truth table of Clocked D flip flop CP D Qn+1 0 X Qn 1 0 0 1 1 1 Fig. 5.17 Clocked D Flip Flop The output does not exist when the clock when the clock pulse absent. Q n is the binary state (present state) of the flip flop before the occurrence of a clock pulse. It is known as present state. Qn+1 is the state of the flip flop after the occurrence of a clock pulse which is known as next state. 5.11.4 JK Flip flop A JK flip flop is a refinement of the RS flip flop. In JK Flip flip the unpredictable state in the RS flip flop is defined inputs J and K behave like inputs S and R to set and reset the flip flop respectively as shown in fig. Case 1: When J and K both AND gates are disabled. Therefore, clock pulses have no effect and, Q and Q̄retain their last values. The truth table of JK FF as shown in Table. Table 5.16 Truth table of Clocked JK flip flop CP J K Qn+1 1 0 0 Qn 1 0 1 0 1 1 0 1 1 1 1 toggle Truth table of Clocked JK flip flop Fig. 5.18 Logic circuit for Clocked JK Flip Flop Case 2: When J is high and K is low, the upper gate is disabled. So there is no way to set the flip flop. The only possibility is reset. When K is high the upper gate passes a Reset trigger as shown as shown as the next possible clock pulse arrives. The forces Q to become low. Therefore J = 0 and K = 1means that the next positive clock clock pulse resets the flip flop unless Q is already reset. Case 3: When J is high and K is low, the upper gate is disabled, so there is no way to reset the flip flop. The only possibility is to set the flip; flop if it not previously set with Q = 0, Q is high and hence the lower gate passes a SET trigger on the next positive clock pulse. This drives Q into the high state. Therefore, J = 1 and K = 0 means that the next positive clock pulse set the flip flop unless Q is already set. Case 4: When J and K bith are high ( Recall that this is an indeterminate condition with an RS flip flop) it’s possible to set or reset the flip flop. If Q is high, the upper gate passes a REAET trigger on thse next positive clock edge. On the otherhand, when Q is low, the lower gate passes a SET trigger on the next positive clock edge. Either way, Q changes to the complement of the last state. Therefore, J = K = 1 means output of the flip flop will toggle will on the next positive clock edge. 5.11.5 T – FLIP FLOP When the two inputs of JK FF are shorted, the T – FF is formed. The symbol of T – FF is shown below. Table 5.17 Truth Table of Clocked T flipflop T Q 0 No change 1 complement The T – FF is named so, because of its ability to “Toggle” (or change or complement) its state. When the T input is 0, the FF state does not have any change. But when T = 1,the state of FF complements. 5.12 COUNTER A counter is used to count the number of clock pulses given. A counter is constructed by chain of flip flops. These flip flops go through the sequence of states, when pulses are applied to its clock inputs. This is the main difference between a register and a counter. ( The counter is used to count the number of clock pulse through the sequence may be ascending, descending and non sequence). Classification Counter There are two types of counters 1. Synchronous counter In synchronous counter, the common clock input is connected to the flip flops and all the flip flops are clocked simultaneously. 2. Asynchronous counter In asynchronous counter (called ripple counter), the first flip flop is clocked by the external clock pulse and each successive flip flops are clocked from the previous flip flop outputs (may Q or Q̄ ).therefore the asynchronous counter is not clocked simultaneously. Synchronous Vs Asynchronous Counter Sl.No. Synchronous counter Asynchronous counter 1 2 3 4 In this type of counters there is no connection of first flip flop output to clock input of the next flip flop. All the flip flops are clocked simultaneously. Designing of logic circuits becomes complex for more number of states. High speed In this counter flip flops are connected in such a way that the first flip flop output is used as a clock for the next flip flop All the flip flops are not clocked simultaneously. Design is very simple even for more number of states Low speed 5.12.1 RIPPLE COUNTER (ASYNCHRONOUS COUNTER) If starting from the initial state, the counter returns to the initial state after completed sequence of the input wave form, the counter is called as modulo ( modulus n) counter or a base r counter. The ripple counter as shown in fig with timing diagram. Three JK flip flops are connected for the toggling mode (J = K = 1 (or) connected with +5V) the timing diagram shown in fig. As per the definition the first flip flop is clocked by the external clock pulse and remaining flip flops are clocked by using the previous flip flop outputs. We assume that the flip flops toggle on the negative going transition of the wave form at the clock input. Each flip flop changes the state when the preceding flip flop or input wave form makes changes from logic 0. Considering the initial state Q AQBQC = 0 0 0. The count sequence 001,010,011,100,101,110,111) of the counter can be Fig 5.18 Three bit Ripple Counter read simply (000, Fig. 5.19 Timing diagram for 3 bit Ripple Counter 5.12.2 ASYNCHRONOUS BCD COUNTER Counters can be designed to have a number of states in their sequence that is less than 2n. the resulting sequence is called a truncated sequence. One common modulus for counters with truncated sequence is ten. Such counters are referred to as decade counters. Furthermore, a counter which counts a sequence of zero (0000) through nine (1001) is referred to as a BCD decade counter because its ten state sequence is the BCD code. To obtain a truncated sequence it is necessary to force the counter to cycle before going through all of its normal states. For example, the BD decade counter must recycle back to the state 0000 after state 1001. Note that a decade counter will require 4 flip- flops. One method that can be used to achieve recycling after the count of nine (1001) is to decode ten (1010) with a NAND gate and connected the output of the NAND gate to the clear inputs of all the flip-flops as illustrated in fig. Notice that only Q2 and Q4 are connected to the NAND gate inputs. This arrangement is an example of partial decoding, in which two unique states (Q 2 = 1 and Q4 = 1) are enough to decode the count of 1010. This is because none of the other states (zero through nine) have Q2 and Q4 high at the same time. Consequently, when the counter goes into count ten (1010) the decoding gate output goes output goes LOW and asynchronous Reset all of the flip flops. Fig. 5.20 An asynchronous BCD Counter 5.12.3 UP/DOWN SYNCHRONOUS COUNTER An up/down couter is one that is capable of processing in ascending order or descending order through a certain sequence. An up/down counter is also called bidirectional counter. Usually up/down operation of the counter is controlled by UP/ D̄Ō¯W̄¯N̄ signal. When this signal is HIGH, counter goes through UP sequence, i.e., 0, 1, 2, 3, n.when UP/ D̄Ō¯W̄N̄¯ singal is LOW counter follows reverse sequence i.e., n, n1, n-2, ……..,1,0. For 3-bit counters these sequence are: 0,1,2,3,4,5,6,7 for up sequence and 7,6,5,4,3,2,1,0 for down sequence. Table 5.18 Three bit UP/DOWN counter Table CP UP QC QB QA 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 DOWN Fig. 5.21 Logic diagram for synchronous Up/Down counter The arrow in the Table indicate the state- to- state movement of the counter for both its UP and its DOWN modes of operation. Figure shows the three bit up/down counter. 5.13 SHIFT REGISTER A register that is capable of shifting data one bit at a time is called a shift register. The logical configuration of a serial shift register consists of a chain of flipflops connected in cascade, with the output of one flip flop being connected to the input of its neighbor. The operation of the shift register is synchronous; thus each flip flop is connected to a common clock. Using D flip-flops forms the simplest type of shiftregisters. The basic data movement possible within a four-bit shift register is shown in fig. Fig. 5.22 Data movement diagram Figure shows the circuit diagram for a four- bit serial in-serial out shift register implemented using D flip-flops. Assuming that the register is initially clear. Fig. 5.23 Four-bit serial in-serial out shift register a) Shift left register Figure shows shift left register. We will illustrate the entry of the four bit binary number 1111 into the register beginning with the right most. Fig. 5.24 Logic Diagram for Shift Left Register Case 1 Initially, register is cleared. So Q A Q B Q C QD = 0 0 0 0 When the data 1 1 1 1 is applied serially. The left most 1 is applied to Din Din = 1, QD QC QB QA = 0 0 0 0 The arrival of the first falling clock edges sets the right most (D flip flop) and the stored information as follws Q D Q C Q B QA = 0 0 0 1 Case 2 When the next negative clock edges hits, the flip flop sets and the register contents Q D Q C Q B QA = 0 0 1 1 Case 3 The third negative clock edges, the register contents Q D Q C Q B QA = 0 1 1 1 Case 4 The fourth negative clock edges, the register contents Q D Q C Q B QA = 1 1 1 1 b) Shift right register Figure shows serial in serial out shift right register. The entry (consider the binary data 1 1 1 1) of the four bit binary number into the register, beginning with the left most bit, the register is cleared Fig. 5.25 4-bit Shift Right Register QD Q C Q B QA = 0 0 0 0 When the data 1 1 1 1 is applied serially the left most 1 is applied to Din So, Din = 1 Q D Q C Q B QA = 0 0 0 0 Case 1 The arrival of the first falling clock edge sets the left most flip flop, And stored contents as follows Q D Q C Q B QA = 1 0 0 0 Case 2 After second falling clock edge, the register contents Q D Q C Q B QA = 1 1 0 0 Case 3 The third falling clock edge, the register contents Q D Q C Q B QA = 1 1 1 0 Case 4 The fourth falling clock edge, the register contents Q D Q C Q B QA = 1 1 1 1 5.13.1 SERIAL-IN, PARALLEL-OUT SHIFT REGISTER Figure shows the logic diagram and the logic symbol of a 4-bit serial-in, parallelout, shift register. In this type of register, the data bits are entered into the register serially, but the data stored in the register is shifted out in parallel form. Once the data bits are stored, each bit appears on its respective output line and all bits are available simultaneously, rather than on a bit-by-bit basis as with the serial output. The serial-in, parallel-out, shift register can be used as a serial-in, serial out, shift register if the output is taken from the Q terminal of the last FF. Fig. 5.26 Serial in parallel- out Shift Register 5.13.2 PARALLEL-IN, SERIAL-OUT SHIFT REGISTER For a parallel-in, serial-out, shift register, the data bits are entered simultaneously into their respective stages on parallel lines, rather than on a bit- bybit basis on one line as with serial data inputs, but the data bits are transferred out of the register serially, i.e. on a bit-by-bit basis over a single line. Figure 5.26 illustrates a 4-bit parallel-in, serial-out, shift register using D FFs. There are four data lines A, B, C and D through which the data is entered into the register in parallel form. The signal Shift/LOAD allows (a) the data to be entered in parallel form into the register and (b) the data to be shifted out serially from terminal Q4. When Shift / L̄ŌĀ¯D̄ line is HIGH, gates G1, G2 and G3 are disabled, but gates G4,G5 and G6 are enabled allowing the data bits to shift-right from one stage to the next. When Shift/L̄¯ŌĀ¯D̄ line is LOW, gates G4, G5 and G6 are disabled, whereas gates G1 , G2 and G3 are enabled allowing the data input to appear at the D inputs of the respective FFs. When a clock pulse is applied, these data OR gate allows either the normal shifting operation of the parallel data entry depending on which AND gates are enable by the level on the Shift/L̄¯ŌĀ¯D̄ input. Fig. 5.27 Parallel – in, Serial- out Shift Register 5.13.3 PARALLEL- IN, PARALLEL-OUT SHIFT REGISTER In a parallel-in, parallel-out, shift register, the data is entered into the register in parallel form and also the data is taken out of the register in parallel form. Immediately following the simultaneous entry of all data bits, the bits appear on the parallel outputs. Figure shows a 4-bit parallel-in, parallel-out, shift register using D FFs. Data is applied to the D input terminals of the FFs. When a clock pulse is applied, at the positive-going edge of that pulse, the D inputs are shifted into the Q output of the FFs. The register now stores data is available instantaneously for shifting out in parallel form. Fig. 5.28 Parallel-in, Parallel-out Shift Register