University:
Massachusetts Institute of Technology
Course:
6.012 | Microelectronic Devices and Circuits
Academic year:

2024
Views:

246

Pages:

20
Author:

toonioumem6z

Lecture 10 MOSFET (II) MOSFET IV Characteristics (cont.) October 13, 2005 Contents: 1. The saturation regime 2. Backgate characteristics Reading assignment: Howe and Sodini, Ch. 4, §4.4 Announcements: Quiz 1: 10/13, 7:309:30 PM, (lectures #19); open book; must have calculator. Key questions • How does the MOSFET work in saturation? • Does the pinchoﬀ point represent a block to current ﬂow? • How come the MOSFET current still increases a bit with VDS in saturation? • How does the application of a back bias aﬀect the MOSFET IV characteristics? 1. The saturation regime Geometry of problem: y 0 L VDS VGS n+ S -tox 0 ID G IS D n+ xj n+ inversion� layer VBS=0 depletion� region p B x Regimes of operation so far (VBS = 0): • Cutoﬀ: VGS < VT , VGD < VT : no inversion layer anywhere underneath gate ID = 0 • Linear: VGS > VT , VGD > VT (with VDS > 0): inversion layer everywhere underneath gate VDS W ID = µnCox (VGS − − VT )VDS L 2 Output characteristics: ID VDS=VGS-VT VGS VGS=VT 0 0 VDS � Review of Qn, Ey , Vc , and VGS − Vc(y) in linear regime as VDS increases: |Qn(y)| VDS=0 Cox(VGS-VT) VDS 0 0 L y |Ey(y)| VDS VDS=0 0 0 L y Vc(y) VDS VDS VDS=0 0 L 0 y VGS-Vc(y) VDS=0 VDS VGS VDS local gate� overdrive VT 0 L y Ohmic drop along channel debiases inversion layer ⇒ ID rises more slowly with VDS � Drain current saturation As VDS approaches: VDSsat = VGS − VT increase in |Ey | compensated by decrease in |Qn| ⇒ ID saturates to: IDsat = IDlin(VDS = VDSsat = VGS − VT ) Then: W IDsat = µnCox(VGS − VT )2 2L VDSsat=VGS-VT ID linear saturation VGS VGS=VT 0 0 cutoff VDS W IDsat = µnCox(VGS − VT )2 2L Transfer characteristics in saturation: ID VDS>VDSsat=VGS-VT 0 0 VT VGS � What happens when VDS = VGS − VT ? Charge control relation at drainend of channel: Qn(L) = −Cox(VGS − VDS − VT ) = 0 No inversion layer at end of channel??!! ⇒ Pinchoﬀ At pinchoﬀ: • charge control equation inaccurate around VT • electron concentration small but not zero • electrons move fast because electric ﬁeld is very high • dominant electrostatic feature: acceptor charge • there is no barrier to electron ﬂow (on the contrary!) �� G D - - + - - - - - - - ++ +++ +++++ -- - - - inversion layer n+ drain p depletion regions L y � Key dependencies of IDsat • IDsat ∝ (VGS − VT )2 Voltage at pinchoﬀ point (Vc = 0 at source): G - �� D - - -- - - - p + -+ n+ ++++ +++++ -- - - - Vc(L)=VDSsat=VGS-VT Drain current at pinchoﬀ: ∝ lateral electric ﬁeld ∝ VDSsat = VGS − VT ∝ electron concentration ∝ VGS − VT ⇒ IDsat ∝ (VGS − VT )2 • IDsat ∝ 1 L L ↓ → |Ey | ↑ 3µm nchannel MOSFET Output characteristics (VGS = 0 − 4 V, ΔVGS = 0.5 V ): Transfer characteristics in saturation (VDS = 3 V ): � What happens if VDS > VGS − VT ? Depletion region separating pinchoﬀ point and drain widens (just like in reversebiased pn junction) G �� D - - - - -+ + n+ - - - ++++ +++++ -- - - - Vc(L-ΔL)=VDSsat=VGS-VT p L-ΔL L y To ﬁrst order, ID does not increase past pinchoﬀ: W ID = IDsat = µnCox (VGS − VT )2 2L To second order, electrical channel length aﬀected (”channellength modulation”): VDS ↑⇒ Lchannel ↓⇒ ID ↑ 1 1 ΔL ) ID ∝ � (1 + L − ΔL L L Experimental ﬁnding: ΔL ∝ VDS − VDSsat Hence: ΔL = λ(VDS − VDSsat) L Improved model in saturation: W IDsat = µnCox (VGS − VT )2 [1 + λ(VDS − VDSsat)] 2L VDSsat ID VGS VGS=Vth 0 0 VDS Also, experimental ﬁnding: 1 λ∝ L 2. Backgate characteristics There is a fourth terminal in a MOSFET: the body. What does the body do? VDS ID VGS>VT G S D n+ n+ inversion layer VBS depletion region p 0 L y B Body contact allows application of bias to body with re spect to inversion layer, VBS . Only interested in VBS < 0 (pn diode in reverse bias). Interested in eﬀect on inversion layer ⇒ examine for VGS > VT (keep VGS constant). Application of VBS < 0 increases potential buildup across semiconductor: −2φp ⇒ −2φp − VBS Depletion region must widen to produce required extra ﬁeld: ρ xdmax(VBS) 0 0 x -tox -qNa Qn E Eox VBS=0 Es 0 -tox VBS<0 x 0 xdmax(VBS) φ Vox VGS+φB 0 VBS -tox -φp 0 x VB=-2φp VB=-2φp-VBS Consequences of application of VBS < 0: • −2φp ⇒ −2φp − VBS • |QB | ↑⇒ xdmax ↑ • since VGS constant, Vox unchanged ⇒ Eox unchanged ⇒ |Qs| = |QG| unchanged • |Qs| = |Qn| + |QB | unchanged, but |QB | ↑ ⇒ |Qn| ↓ ⇒ inversion layer charge is reduced! Application of VBS < 0 with constant VGS reduces elec tron concentration in inversion layer ⇒ VT ↑ How does VT change with VBS ? In VT formula change −2φp to −2φp − VBS : VTGB (VBS ) � = VF B − 2φp − VBS + γ (−2φp − VBS ) In MOSFETs, interested in VT between gate and source: VGB = VGS − VBS ⇒ VTGB = VTGS − VBS Then: VTGS = VTGB + VBS And: VTGS (VBS ) � = VF B − 2φp + γ (−2φp − VBS ) ≡ VT (VBS ) In the context of the MOSFET, VT is always deﬁned in terms of gatetosource voltage. Deﬁne: VT o = VT (VBS = 0) Then: � � VT (VBS ) = VT o + γ( −2φp − VBS − −2φp ) ID VBS saturation cut-off 0 0 VT VGS Backate characteristics (VBS = 0, −1, −2, −3 V, VDS = 3 V ): Key conclusions • MOSFET in saturation (VDS ≥ VDSsat): pinchoﬀ point at drainend of channel – electron concentration small, but – electrons move very fast; – pinchoﬀ point does not represent a barrier to elec tron ﬂow • In saturation, ID saturates: IDsat = W µnCox(VGS − VT )2 2L • But..., due to channellength modulation, IDsat in creases slightly with VDS • Application of back bias shifts VT (backgate eﬀect)