BJT Biasing

Bipolar Junction Transistor Circuits Biasing. BJT Operating Regimes. Let’s start by reviewing the operating regimes of the BJT. They are graphically shown on Figure 1 along with the device schematic and relevant parameters. IC Saturation Breakdown IB4 Active C IB3 IC IB2 + V CE - B IB1 IB=0 Cutoff IB + V BE - IE E VCE Figure 1. BJT characteristic curve The characteristics of each region of operation are summarized below. 1. cutoff region: B-E junction is reverse biased. No current flow 2. saturation region: B-E and C-B junctions are forward biased Ic reaches a maximum which is independent of IB and β. VCE < VBE . No control. 3. active region: B-E junction is forward biased, C-B junction is reverse biased VBE < VCE < VCC , I C = β I B . Control 4. breakdown region: I C and VCE exceed specifications damage to the transistor 22.071/6.071 Spring 2006, Chaniotakis and Cory 1 We will focus on operation in the active region. In this region of operation the model of the BJT is shown on Figure 2 C IC β IB B IB V BE E Figure 2. Large signal model of the BJT operating in the active region The large signal model represents a simple state machine. The two states of interest are: 1. B-E junction is forward biased, VBE = 0.7 Volts, current flows and the BJT is on 2. B-E junction is off, no current flows and the BJT is off. We are interested in using the transistor as an amplifier with amplification A as shown on Figure 3 for which V0 = AVI VI A V0 Figure 3. Amplifier symbol For the generic BJT circuit the voltage transfer characteristic curve (output voltage versus input voltage) is shown on Figure 4. For amplification, the transistor must operate in the active or linear region. 22.071/6.071 Spring 2006, Chaniotakis and Cory 2 V0 Cutoff Active regime (large slope) amplification Saturation VCE(sat) VBE(on) VI Figure 4. Voltage transfer curve for BJT circuit This presents a challenge since we normally have a signal that is carried by, for example, a time dependent voltage which is permitted to go to (or through) zero. Now we can not simply apply this voltage to the base since the transistor would be moving in and out of the linear operation region. Consider the amplifier circuit of Figure 5. We will qualitatively investigate the voltage transfer characteristics of this circuit for two cases of the input signal VI . These two cases are graphically illustrated on Figure 6 (a) and (b). VCC RC IC Vo V1 RB IB Figure 5. Amplifier circuit The fluctuations of the input signal on Figure 6(a) result in excursions outside the active region of operation. As shown on the plot a portion of the signal is clipped. Compare this to the case shown on Figure 6 (b). Here the input signal has been shifted to the middle of the 22.071/6.071 Spring 2006, Chaniotakis and Cory 3 active region and as a result the fluctuations of the input are within the range of operation and the complete amplified signal appears at the output. Clipped signal VBE(on) V0 Active region t VI t (a) V0 VBE(on) Active region t t VI (b) Figure 6. Therefore, the simple solution is to offset the input voltage to the middle of the linear response region. In this way the system may accept input voltage fluctuations and still 22.071/6.071 Spring 2006, Chaniotakis and Cory 4 remain in the active region of operation. This offsetting of base voltage is called biasing and we will next investigate various circuit configurations that accomplish this task. The Q-Point The Quiescent Q-point corresponds to a specific point on the load line. The amplifier operates at the Q-point when the amplitude of the time varying signal is zero. This is shown on the characteristic curve shown on Figure 7. V0 VBE(on) Q-Point VI Figure 7 The Q-point may also be represented on the I C versus VCE characteristic plot as shown on Figure 8. Here the Q-point is at the intersection of the load line with one of the operating curves of the transistor. IC Load line Q-point IC(sat) Ib4 IB3 IB2 IB1 VCC VCE Figure 8 22.071/6.071 Spring 2006, Chaniotakis and Cory 5 In fact the Q-point could be at any of the intersection points between the load line and the transistor curves. We have chosen the Q-point corresponding to I B 2 on the plot of Figure 8 since that point is at about the midpoint of the load line. In amplifier design applications the Q-point corresponds to DC values for I C and VCE that are about half their maximum possible values as illustrated on Figure 9. This is called midpoint biasing and it represents the most efficient use of the amplifiers range for operation with AC signals. The range that the input signal can assume is the maximum and no clipping of the signal can occur (assuming that the signal range is less than the maximum available) IC Q-point IC(sat) ICQ VCEQ VCC VCE Figure 9. Q-point for midpoint biasing BJT Bias Types Base Bias. Consider the circuit shown on Figure 10. VCC RC RB V0 vi Figure 10. Base bias circuit 22.071/6.071 Spring 2006, Chaniotakis and Cory 6 The DC operating point (Q-point) for this circuit is determined independent of the signal source vi. (We have indicated the AC signal by the lower case v in order to distinguish it from the DC operating point indicated by the capital V) The DC current into the base may be determined by voltage around the base-emitter loop which gives VCC = I B RB + VBE (1.1) and the DC base current becomes IB = VCC − VBE RB (1.2) For operation in the active region, IC = β I B = β VCC − VBE RB (1.3) Consideration of the collector-emitter loop gives VCC = I C RC + VCE (1.4) And the collector current is IC = VCC − VCE RC (1.5) Equation (1.5) is the load line equation for this circuit and it along with Equation (1.3) define the Q point. We see that the Q-point for the Base-bias configuration depends on the β value of the transistor. The β value is an imprecise quantity and it is also a quantity whose value changes with temperature. Therefore, the Q-point will shift around as β changes which is not a desirable characteristic of the design. DO NOT DESIGN WITH β 22.071/6.071 Spring 2006, Chaniotakis and Cory 7 Voltage Divider Bias. Next let’s consider the circuit shown on Figure 11. Here we have used a voltage divider network at the base of the transistor and we have also added resistor RE at the emitter. The capacitor C is called the coupling capacitor and it provides DC isolation between the amplifier and the signal source vi. Therefore the role of the coupling capacitor is to suppress all DC components that might be present in the signal vi. VCC R1 C IC RC A VB V0 IB vi R2 IE RE Figure 11. Voltage divider bias circuit Now we need to take care of the biasing (i.e. the generation of the desirable DC voltage component at the base of the transistor). The most general biasing is to assume that the input signal can be both positive and negative. So, for vi= 0, set the output voltage, V0 = VCC / 2 (mid range). To find the base voltage corresponding to this set point we need to focus on the currents in the circuit. Recall that the defining equation for the BJT operation is given in terms of currents ( I C = β I B ) . If V0 = VCC / 2 then the voltage drop across RC must also be VCC / 2 and the quiescent current is I CQ = VCC 2 RC (1.6) Now the design is nearly set. Given the collector current, and knowing that we are in the linear region of operation, the base current is given by 22.071/6.071 Spring 2006, Chaniotakis and Cory 8 I BQ = I CQ β (1.7) V = CC 2 β RC In DC, the Thevenin equivalent circuit to the left of point A is represented by the equivalent circuit shown on Figure 12 for which RTH = R1 R2 R1 + R2 (1.8) And VTH = VCC R2 R1 + R2 (1.9) VCC RC RTH A I CQ V0 VB I BQ VTH I EQ RE Figure 12 KVL around the base-emitter loop gives VTH = I BQ RTH + VBE ( on ) + I EQ RE (1.10) Since the transistor is operating in the active region the emitter current is I EQ = (1 + β ) I BQ (1.11) And so from Equation (1.10) the base current becomes 22.071/6.071 Spring 2006, Chaniotakis and Cory 9 I BQ = VTH − VBE ( on ) RTH + (1 + β ) RE (1.12) And finally the quiescent collector current becomes I CQ = β I BQ = β (VTH − VBE ( on ) ) RTH + (1 + β ) RE (1.13) Our goal is to design a stable quiescent point. This is equivalent to having the quiescent point be independent of the β παραµετερ. From Equation (1.13) we see that if RTH << (1 + β ) RE then I CQ ≅ β (VTH − VBE ( on ) ) (1 + β ) RE (1.14) And for β >> 1 I CQ ≅ VTH − VBE ( on ) RE (1.15) In practice making RTH small is limited by power dissipation in resistors R1 and R2 . A general acceptable design rule is to have RTH = 22.071/6.071 Spring 2006, Chaniotakis and Cory 1 (1 + β ) RE 10 (1.16) 10 The quiescent collector-emitter voltage VCE is found from the load line equation which is obtained by considering the C-E loop VCEQ = VCC − I CQ RC − I EQ RE = VCC − I CQ RC − Which for β >> 1 becomes 1+ β β I CQ RE (1.17) ⎛ ⎞ 1+ β RE ⎟ = VCC − I CQ ⎜ RC + β ⎝ ⎠ VCEQ ≅ VCC − I CQ ( RC + RE ) (1.18) The Q-point is thus defined by Equations (1.15) and (1.18). We have thus derived the conditions for obtaining a stable Q-point (no β dependence) using the voltage divider bias. Equation (1.18) also shows that the effective load resistance seen by the DC collector circuit is RC + RE 22.071/6.071 Spring 2006, Chaniotakis and Cory 11 Now let’s consider the small signal gain of the amplifier. Recall that the transistor operates in the active (linear) region and at the Q-point, the B-E loop and the C-E loop give respectively VTH = I BQ RTH + VBE ( on ) + I EQ RE (1.19) VCEQ = VCC − I CQ RC − I EQ RE (1.20) If a small signal vi is superimposed on the input of the circuit shown on Figure 12 the corresponding circuit is shown on Figure 13. VCC RC RTH IC V0Q + vo VB IB vi IE RE VTH Figure 13 The output signal is now a superposition of the Q-point and the signal vi. Therefore the B-E loop KVL gives vi = ib RTH + vbe + ie RE (1.21) ib RC + vce + ie RE = 0 (1.22) And the C-E loop gives Where the parameters ie , ib , vce are due to the small signal and vbe = 0 since the transistor is already on and the junction voltage is constant. The voltage gain of the device is the ratio 22.071/6.071 Spring 2006, Chaniotakis and Cory 12 vo β ib RC =− ( β + 1)ib RE + ib RTH vi =− β RC (1.23) ( β + 1) RE + RTH Recall that for Q-point stability we have constrained RTH << (1 + β ) RE and thus for large β the gain reduces to vo R ≅− C vi RE (1.24) So the device has a constant gain and it is an inverter. A question arises naturally by observing the gain Equation (1.24): What happens when RE becomes zero. Before making any conclusions on the value of the gain we must consider the details of the base-emitter junction. This is a diode junction and it has an effective resistance given by kT q rBE = iE (1.27) The temperature dependence of this resistance makes it a very poor parameter to fely upon on a design (unless we desire to measure temperature by exploiting this dependence). Therefore we normally require an emitter resistor RE > rE . 22.071/6.071 Spring 2006, Chaniotakis and Cory 13