University:
California State University, Northridge
Course:
COMP 222 | Computer Organization
Academic year:

2024
Views:

92

Pages:

16
Author:

Layla Bonilla

Chapter 12 Processor Structure and Function Part 4 MMX Register Mapping • MMX uses several 64 bit data types • Use 3 bit register address fields —8 registers • No MMX specific registers —Aliasing to lower 64 bits of existing floating point registers Mapping of MMX Registers to Floating-Point Registers Pentium Interrupt Processing • Interrupts —Maskable —Nonmaskable • Exceptions —Processor detected —Programmed • Interrupt vector table —Each interrupt type assigned a number —Index to vector table —256 * 32 bit interrupt vectors • 5 priority classes ARM Attributes • RISC • Moderate array of uniform registers — More than most CISC, less than many RISC • Load/store model — Operations perform on operands in registers only • Uniform fixed-length instruction — 32 bits standard set 16 bits Thumb • Shift or rotation can preprocess source registers — Separate ALU and shifter units • Small number of addressing modes — All load/store addressees from registers and instruction fields — No indirect or indexed addressing involving values in memory • Auto-increment and auto-decrement addressing — Improve loops • Conditional execution of instructions minimizes conditional branches Simplified ARM Organization ARM Processor Organization • Many variations depending on ARM version • Data exchanged between processor and memory through data bus • Data item (load/store) or instruction (fetch) • Instructions go through decoder before execution • Pipeline and control signal generation in control unit • Data goes to register file — Set of 32 bit registers — Byte & halfword twos complement data sign extended • Typically two source and one result register • Rotation or shift before ALU ARM Processor Modes • User • Privileged —6 modes – OS can tailor systems software use – Some registers dedicated to each privileged mode – Swifter context changes • Exception —5 of privileged modes —Entered on given exceptions —Substitute some registers for user registers – Avoid corruption Privileged Modes • System Mode — Not exception — Uses same registers as User mode — Can be interrupted by… • Supervisor mode — OS — Software interrupt usedd to invoke operating system services • Abort mode — memory faults • Undefined mode — Attempt instruction that is not supported by integer core coprocessors • Fast interrupt mode — Interrupt signal from designated fast interrupt source — Fast interrupt cannot be interrupted — May interrupt normal interrupt • Interrupt mode • Interrupt signal from any other interrupt source ARM Register Organization User Table Modes Privileged modes Exception modes System Supervisor Abort Undefined Interrupt Fast Interrupt R0 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8 R8_fiq R9 R9 R9 R9 R9 R9 R9_fiq R10 R10 R10 R10 R10 R10 R10_fiq R11 R11 R11 R11 R11 R11 R11_fiq R12 R12 R12 R12 R12 R12 R12_fiq R13 (SP) R13 (SP) R13_svc R13_abt R13_und R13_irq R13_fiq R14 (LR) R14 (LR) R14_svc R14_abt R14_und R14_irq R14_fiq R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) CPSR CPSR CPSR CPSR CPSR CPSR CPSR SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq ARM Register Organization • 37 x 32-bit registers • 31 general-purpose registers —Some have special purposes —E.g. program counters • Six program status registers • Registers in partially overlapping banks —Processor mode determines bank • 16 numbered registers and one or two program status registers visible General Register Usage • R13 normally stack pointer (SP) —Each exception mode has its own R13 • R14 link register (LR) —Subroutine and exception mode return address • R15 program counter CPSR • CPSR process status register —Exception modes have dedicated SPSR • 16 msb are user flags —Condition codes (N,Z,C,V) —Q – overflow or saturation in some SMID instructions —J – Jazelle (8 bit) instructions —GEE[3:0] SMID use [19:16] as greater than or equal flag • 16 lsb system flags for privilege modes —E – endian —Interrupt disable —T – Normal or Thumb instruction —Mode ARM CPSR and SPSR ARM Interrupt (Exception) Processing • • • • More than one exception allowed Seven types Execution forced from exception vectors Multiple exceptions handled in priority order • Processor halts execution after current instruction • Processor state preserved in SPSR for exception —Address of instruction about to execute put in link register —Return by moving SPSR to CPSR and R14 to Foreground Reading • Processor examples • Stallings Chapter 12 • Manufacturer web sites & specs