University:
California State University, Northridge
Course:
COMP 222 | Computer Organization
Academic year:

2024
Views:

186

Pages:

19
Author:

colobdkaorio0h

Chapter 7 Input/Output Part 2 Identifying Interrupting Module (1) • Different line for each module —PC —Limits number of devices • Software poll —CPU asks each module in turn —Slow Identifying Interrupting Module (2) • Daisy Chain or Hardware poll —Interrupt Acknowledge sent down a chain —Module responsible places vector on bus —CPU uses vector to identify handler routine • Bus Master —Module must claim the bus before it can raise interrupt —e.g. PCI & SCSI Multiple Interrupts • Each interrupt line has a priority • Higher priority lines can interrupt lower priority lines • If bus mastering only current master can interrupt Example - PC Bus • 80x86 has one interrupt line • 8086 based systems use one 8259A interrupt controller • 8259A has 8 interrupt lines Sequence of Events • • • • • • 8259A accepts interrupts 8259A determines priority 8259A signals 8086 (raises INTR line) CPU Acknowledges 8259A puts correct vector on data bus CPU processes interrupt ISA Bus Interrupt System • ISA bus chains two 8259As together • Link is via interrupt 2 • Gives 15 lines —16 lines less one for link • IRQ 9 is used to re-route anything trying to use IRQ 2 —Backwards compatibility • Incorporated in chip set 82C59A Interrupt Controller Intel 82C55A Programmable Peripheral Interface Using 82C55A To Control Keyboard/Display Direct Memory Access • Interrupt driven and programmed I/O require active CPU intervention —Transfer rate is limited —CPU is tied up • DMA is the answer DMA Function • Additional Module (hardware) on bus • DMA controller takes over from CPU for I/O DMA Module Diagram DMA Operation • CPU tells DMA controller:- —Read/Write —Device address —Starting address of memory block for data —Amount of data to be transferred • CPU carries on with other work • DMA controller deals with transfer • DMA controller sends interrupt when finished DMA Transfer Cycle Stealing • DMA controller takes over bus for a cycle • Transfer of one word of data • Not an interrupt —CPU does not switch context • CPU suspended just before it accesses bus —i.e. before an operand or data fetch or a data write • Slows down CPU but not as much as CPU doing transfer Aside • What effect does caching memory have on DMA? • Hint: how much are the system buses available? DMA Configurations (1) • Single Bus, Detached DMA controller • Each transfer uses bus twice —I/O to DMA then DMA to memory • CPU is suspended twice DMA Configurations (2) • Single Bus, Integrated DMA controller • Controller may support >1 device • Each transfer uses bus once —DMA to memory • CPU is suspended once DMA Configurations (3) • Separate I/O Bus • Bus supports all DMA enabled devices • Each transfer uses bus once —DMA to memory • CPU is suspended once