University:
Brown University
Course:
PHYS 0050 | Foundations of Mechanics
Academic year:

2024
Views:

217

Pages:

14
Author:

Jabin F.

# Universal logic-gate.- NAND (AND-Invert):- NOT gate at output of AND 2. NOR (OR- invert) NOT-gate at output of OR Truth table add Karo Complement lo Special logic gate:- 1. Exclusive OR: (XOR), (CTRL-invertor) Odd parity detector Conclusion logic Gate Using NAND minimum NOT Buffer AND- OR NOR YOR XNOR 5 NAND 1 - logic Gate using NOR minimuly NOT - Byffer AND 3 OR NAND XOR 2 14 S YNOR 4 NOR - #Exclusive NOR: (XNOR, even parity detector CTRL Buffer, equality detector, Coincidence detector, gate of equivalence) Associative law: (3imput) Gate 1. (a+b)+C = a+(b+c) OR 2. (9.6).C = a.(6.6) 3. (ab) c = a (bc) 4. (906)OC = 00(60c) S a.b.c = a. b.c 6. a+b+c = a+b+c AND XOR XNOR NAND gate does. not follow associative law. NOR gate does not follow Associ- Law.