Computer Organization and Architecture Study Materials

The IAS Instruction Set Instruction Type Opcode 00001010 Symbolic Representation LOAD MQ 00001001 LOAD MQ,M(X) 00100001 STOR M(X) 00000001 00000010 00000011 LOAD M(X) LOAD –M(X) LOAD |M(X)| 00000100 00001101 00001110 00001111 LOAD –|M(X)| JUMP M(X,0:19) JUMP M(X,20:39) JUMP+ M(X,0:19) 00010000 JUMP+ M(X,20:39) 00000101 00000111 00000110 00001000 ADD M(X) ADD |M(X)| SUB M(X) SUB |M(X)| 00001011 MUL M(X) 00001100 DIV M(X) 00010100 LSH 00010101 RSH 00010010 STOR M(X,8:19) 00010011 STOR M(X,28:39) Data transfer Unconditional branch Conditional branch Arithmetic Address modify Description Transfer contents of register MQ to the accumulator AC Transfer contents of memory location X to MQ Transfer contents of accumulator to memory location X Transfer M(X) to the accumulator Transfer –M(X) to the accumulator Transfer absolute value of M(X) to the accumulator Transfer –|M(X)| to the accumulator Take next instruction from left half of M(X) Take next instruction from right half of M(X) If number in the accumulator is nonnegative, take next instruction from left half of M(X) If number in the accumulator is nonnegative, take next instruction from right half of M(X) Add M(X) to AC; put the result in AC Add |M(X)| to AC; put the result in AC Subtract M(X) from AC; put the result in AC Subtract |M(X)| from AC; put the remainder in AC Multiply M(X) by MQ; put most significant bits of result in AC, put least significant bits in MQ Divide AC by M(X); put the quotient in MQ and the remainder in AC Multiply accumulator by 2; i.e., shift left one bit position Divide accumulator by 2; i.e., shift right one position Replace left address field at M(X) by 12 rightmost bits of AC Replace right address field at M(X) by 12 rightmost bits of AC Computer Generations Generation Approximate Dates 1 2 3 1946–1957 1958–1964 1965–1971 4 5 6 1972–1977 1978–1991 1991- Technology Vacuum tube Transistor Small and medium scale integration Large scale integration Very large scale integration Ultra large scale integration Typical Speed (operations per second) 40,000 200,000 1,000,000 10,000,000 100,000,000 1,000,000,000 Key Characteristics of the System/360 Family Characteristic Model 30 Model 40 Model 50 Model 65 Model 75 Maximum memory size (bytes) Data rate from memory (Mbytes/sec) Processor cycle time µs) 64K 0.5 256K 0.8 256K 2.0 512K 8.0 512K 16.0 1.0 0.625 0.5 0.25 0.2 Relative speed Maximum number of data channels Maximum data rate on one channel (Kbytes/s) 1 3 250 3.5 3 400 10 4 800 21 6 1250 50 6 1250 Examples of Embedded Systems and Their Markets [NOER05] Market Automotive Consumer electronics Industrial control Medical Office automation Embedded Device Ignition system Engine control Brake system Digital and analog televisions Set-top boxes (DVDs, VCRs, Cable boxes) Personal digital assistants (PDAs) Kitchen appliances (refrigerators, toasters, microwave ovens) Automobiles Toys/games Telephones/cell phones/pagers Cameras Global positioning systems Robotics and controls systems for manufacturing Sensors Infusion pumps Dialysis machines Prosthetic devices Cardiac monitors Fax machine Photocopier Printers Monitors Scanners ARM Evolution Family ARM1 ARM2 ARM3 ARM6 ARM7 ARM8 Notable Features 32-bit RISC Multiply and swap instructions; Integrated memory management unit, graphics and I/O processor First use of processor cache First to support 32-bit addresses; floatingpoint unit Integrated SoC 5-stage pipeline; static branch prediction ARM9 ARM9E ARM10E ARM11 Cortex XScale Cache Typical MIPS @ MHz None None 7 MIPS @ 12 MHz 4 KB unified 12 MIPS @ 25 MHz 4 KB unified 28 MIPS @ 33 MHz 8 KB unified 8 KB unified 60 MIPS @ 60 MHz 84 MIPS @ 72 MHz 16 KB/16 KB 300 MIPS @ 300 MHz 220 MIPS @ 200 MHz Enhanced DSP instructions 6-stage pipeline 9-stage pipeline 16 KB/16 KB 13-stage superscalar pipeline Applications processor; 7-stage pipeline Variable 740 MIPS @ 665 MHz 2000 MIPS @ 1 GHz 32 KB/32 KB L1 512 KB L2 1000 MIPS @ 1.25 GHz DSP = digital signal processor SoC = system on a chip 32 KB/32 KB Variable Performance Factors and System Attributes Ic p Instruction set architecture X X Compiler technology X X Processor implementation Cache and memory hierarchy m k τ X X X X X