University:
California State University, Northridge
Course:
COMP 122/L | Computer Architecture and Assembly Language and Lab
Academic year:

2024
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412

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51
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dividableyr3

+ Computer Organization and Architecture + Chapter 17 Parallel Processing + Multiple Processor Organization  Single instruction, single data (SISD) stream    Single processor executes a single instruction stream to operate on data stored in a single memory Uniprocessors fall into this category Single instruction, multiple data (SIMD) stream    A single machine instruction controls the simultaneous execution of a number of processing elements on a lockstep basis Vector and array processors fall into this category Multiple instruction, single data (MISD) stream    A sequence of data is transmitted to a set of processors, each of which executes a different instruction sequence Not commercially implemented Multiple instruction, multiple data (MIMD) stream  A set of processors simultaneously execute different instruction sequences on different data sets  SMPs, clusters and NUMA systems fit this category Symmetric Multiprocessor (SMP) A stand alone computer with the following characteristics: Two or more similar processors of comparable capacity Processors share same memory and I/O facilities • Processors are connected by a bus or other internal connection • Memory access time is approximately the same for each processor All processors share access to I/O devices • Either through same channels or different channels giving paths to same devices System controlled by integrated operating All processors system can perform • Provides the same interaction functions between processors and (hence “symmetric”) their programs at job, task, file and data element levels Multiprogramming and Multiprocessing Symmetric Multiprocessor Organization + The bus organization has several attractive features:  Simplicity   Flexibility   Simplest approach to multiprocessor organization Generally easy to expand the system by attaching more processors to the bus Reliability  The bus is essentially a passive medium and the failure of any attached device should not cause failure of the whole system + Disadvantages of the bus organization:   Main drawback is performance  All memory references pass through the common bus  Performance is limited by bus cycle time Each processor should have cache memory   Reduces the number of bus accesses Leads to problems with cache coherence  If a word is altered in one cache it could conceivably invalidate a word in another cache   To prevent this the other processors must be alerted that an update has taken place Typically addressed in hardware rather than the operating system + Multiprocessor Operating System Design Considerations  Simultaneous concurrent processes    Scheduling     With multiple active processes having potential access to shared address spaces or I/O resources, care must be taken to provide effective synchronization Synchronization is a facility that enforces mutual exclusion and event ordering Memory management    Any processor may perform scheduling so conflicts must be avoided Scheduler must assign ready processes to available processors Synchronization   OS routines need to be reentrant to allow several processors to execute the same IS code simultaneously OS tables and management structures must be managed properly to avoid deadlock or invalid operations In addition to dealing with all of the issues found on uniprocessor machines, the OS needs to exploit the available hardware parallelism to achieve the best performance Paging mechanisms on different processors must be coordinated to enforce consistency when several processors share a page or segment and to decide on page replacement Reliability and fault tolerance   OS should provide graceful degradation in the face of processor failure Scheduler and other portions of the operating system must recognize the loss of a processor and restructure accordingly + Cache Coherence Software Solutions  Attempt to avoid the need for additional hardware circuitry and logic by relying on the compiler and operating system to deal with the problem  Attractive because the overhead of detecting potential problems is transferred from run time to compile time, and the design complexity is transferred from hardware to software  However, compile-time software approaches generally must make conservative decisions, leading to inefficient cache utilization + Cache Coherence Hardware-Based Solutions  Generally referred to as cache coherence protocols  These solutions provide dynamic recognition at run time of potential inconsistency conditions  Because the problem is only dealt with when it actually arises there is more effective use of caches, leading to improved performance over a software approach  Approaches are transparent to the programmer and the compiler, reducing the software development burden  Can be divided into two categories:   Directory protocols Snoopy protocols Directory Protocols Collect and maintain information about copies of data in cache Effective in large scale systems with complex interconnection schemes Directory stored in main memory Creates central bottleneck Requests are checked against directory Appropriate transfers are performed Snoopy Protocols  Distribute the responsibility for maintaining cache coherence among all of the cache controllers in a multiprocessor     Suited to bus-based multiprocessor because the shared bus provides a simple means for broadcasting and snooping   A cache must recognize when a line that it holds is shared with other caches When updates are performed on a shared cache line, it must be announced to other caches by a broadcast mechanism Each cache controller is able to “snoop” on the network to observe these broadcast notifications and react accordingly Care must be taken that the increased bus traffic required for broadcasting and snooping does not cancel out the gains from the use of local caches Two basic approaches have been explored:   Write invalidate Write update (or write broadcast) + Write Invalidate  Multiple readers, but only one writer at a time  When a write is required, all other caches of the line are invalidated  Writing processor then has exclusive (cheap) access until line is required by another processor  Most widely used in commercial multiprocessor systems such as the Pentium 4 and PowerPC  State of every line is marked as modified, exclusive, shared or invalid  For this reason the write-invalidate protocol is called MESI + Write Update  Can be multiple readers and writers  When a processor wishes to update a shared line the word to be updated is distributed to all others and caches containing that line can update it  Some systems use an adaptive mixture of both writeinvalidate and write-update mechanisms + MESI Protocol To provide cache consistency on an SMP the data cache supports a protocol known as MESI:  Modified   Exclusive   The line in the cache is the same as that in main memory and is not present in any other cache Shared   The line in the cache has been modified and is available only in this cache The line in the cache is the same as that in main memory and may be present in another cache Invalid  The line in the cache does not contain valid data Table 17.1 MESI Cache Line States MESI State Transition Diagram + Multithreading and Chip Multiprocessors  Processor performance can be measured by the rate at which it executes instructions  MIPS rate = f * IPC   f = processor clock frequency, in MHz IPC = average instructions per cycle  Increase performance by increasing clock frequency and increasing instructions that complete during cycle  Multithreading   Allows for a high degree of instruction-level parallelism without increasing circuit complexity or power consumption Instruction stream is divided into several smaller streams, known as threads, that can be executed in parallel Definitions of Threads and Processes Thread in multithreaded processors may or may not be the same as the concept of software threads in a multiprogrammed operating system Thread is concerned with scheduling and execution, whereas a process is concerned with both scheduling/execution and resource and resource ownership Thread switch • The act of switching processor control between threads within the same process • Typically less costly than process switch Thread: Process: • Dispatchable unit of work within a process • Includes processor context (which includes the program counter and stack pointer) and data area for stack • Executes sequentially and is interruptible so that the processor can turn to another thread • An instance of program running on computer • Two key characteristics: • Resource ownership • Scheduling/execution Process switch • Operation that switches the processor from one process to another by saving all the process control data, registers, and other information for the first and replacing them with the process information for the second Implicit and Explicit Multithreading   + All commercial processors and most experimental ones use explicit multithreading  Concurrently execute instructions from different explicit threads  Interleave instructions from different threads on shared pipelines or parallel execution on parallel pipelines Implicit multithreading is concurrent execution of multiple threads extracted from single sequential program  Implicit threads defined statically by compiler or dynamically by hardware + Approaches to Explicit Multithreading  Interleaved      Fine-grained Processor deals with two or more thread contexts at a time Switching thread at each clock cycle If thread is blocked it is skipped Simultaneous (SMT)  Instructions are simultaneously issued from multiple threads to execution units of superscalar processor  Blocked      Coarse-grained Thread executed until event causes delay Effective on in-order processor Avoids pipeline stall Chip multiprocessing    Processor is replicated on a single chip Each processor handles separate threads Advantage is that the available logic area on a chip is used effectively + Approaches to Executing Multiple Threads + Example Systems Pentium 4  More recent models of the Pentium 4 use a multithreading technique that Intel refers to as hyperthreading  Approach is to use SMT with support for two threads  Thus the single multithreaded processor is logically two processors IBM Power5  Chip used in high-end PowerPC products  Combines chip multiprocessing with SMT   Has two separate processors, each of which is a multithreaded processor capable of supporting two threads concurrently using SMT Designers found that having two two-way SMT processors on a single chip provided superior performance to a single fourway SMT processor Power5 Instruction Data Flow Clusters  Alternative to SMP as an approach to providing high performance and high availability  Particularly attractive for server applications  Defined as:    A group of interconnected whole computers working together as a unified computing resource that can create the illusion of being one machine (The term whole computer means a system that can run on its own, apart from the cluster) Each computer in a cluster is called a node +  Benefits:     Absolute scalability Incremental scalability High availability Superior price/performance + Cluster Configurations Table 17.2 Clustering Methods: Benefits and Limitations + Operating System Design Issues  How failures are managed depends on the clustering method used  Two approaches:    Failover   The function of switching applications and data resources over from a failed system to an alternative system in the cluster Failback   Highly available clusters Fault tolerant clusters Restoration of applications and data resources to the original system once it has been fixed Load balancing    Incremental scalability Automatically include new computers in scheduling Middleware needs to recognize that processes may switch between machines Parallelizing Computation Effective use of a cluster requires executing software from a single application in parallel Three approaches are: Parallelizing complier Parallelized application Parametric computing • Determines at compile time which parts of an application can be executed in parallel • These are then split off to be assigned to different computers in the cluster • Application written from the outset to run on a cluster and uses message passing to move data between cluster nodes • Can be used if the essence of the application is an algorithm or program that must be executed a large number of times, each time with a different set of starting conditions or parameters Cluster Computer Architecture Example 100-Gbps Ethernet Configuration for Massive Blade Server Site +   Clusters Compared to SMP Both provide a configuration with multiple processors to support high demand applications Both solutions are available commercially SMP  Easier to manage and configure  Much closer to the original single processor model for which nearly all applications are written  Less physical space and lower power consumption  Well established and stable Clustering  Far superior in terms of incremental and absolute scalability  Superior in terms of availability  All components of the system can readily be made highly redundant + Nonuniform Memory Access (NUMA)  Alternative to SMP and clustering  Uniform memory access (UMA)     Nonuniform memory access (NUMA)     All processors have access to all parts of main memory using loads and stores Access time to all regions of memory is the same Access time to memory for different processors is the same All processors have access to all parts of main memory using loads and stores Access time of processor differs depending on which region of main memory is being accessed Different processors access different regions of memory at different speeds Cache-coherent NUMA (CC-NUMA)  A NUMA system in which cache coherence is maintained among the caches of the various processors Motivation SMP has practical limit to number of processors that can be used • Bus traffic limits to between 16 and 64 processors NUMA retains SMP flavor while giving large scale multiprocessing In clusters each node has its own private main memory • Applications do not see a large global memory • Coherency is maintained by software rather than hardware Objective with NUMA is to maintain a transparent system wide memory while permitting multiple multiprocessor nodes, each with its own bus or internal interconnect system + CC-NUMA Organization + NUMA Pros and Cons  Main advantage of a CCNUMA system is that it can deliver effective performance at higher levels of parallelism than SMP without requiring major software changes  Bus traffic on any individual node is limited to a demand that the bus can handle  If many of the memory accesses are to remote nodes, performance begins to break down  Does not transparently look like an SMP  Software changes will be required to move an operating system and applications from an SMP to a CC-NUMA system  Concern with availability + Vector Computation  There is a need for computers to solve mathematical problems of physical processes in disciplines such as aerodynamics, seismology, meteorology, and atomic, nuclear, and plasma physics  Need for high precision and a program that repetitively performs floating point arithmetic calculations on large arrays of numbers   Supercomputers were developed to handle these types of problems    Most of these problems fall into the category known as continuous-field simulation However they have limited use and a limited market because of their price tag There is a constant demand to increase performance Array processor   Designed to address the need for vector computation Configured as peripheral devices by both mainframe and minicomputer users to run the vectorized portions of programs Vector Addition Example + Matrix Multiplication (C = A * B) + Approaches to Vector Computation + Pipelined Processing of Floating-Point Operations A Taxonomy of Computer Organizations + IBM 3090 with Vector Facility + Alternative Programs for Vector Calculation + Registers for the IBM 3090 Vector Facility Table 17.3 IBM 3090 Vector Facility: Arithmetic and Logical Instructions + Summary Parallel Processing Chapter 17  Multithreading and chip multiprocessors      Multiple processor organizations  Types of parallel processor systems  Parallel organizations    Organization  Multiprocessor operating system design considerations Cache coherence and the MESI protocol  Software solutions  Hardware solutions  The MESI protocol Clusters   Symmetric multiprocessors     Cluster configurations Operating system design issues Cluster computer architecture Blade servers Clusters compared to SMP Nonuniform memory access     Implicit and explicit multithreading Approaches to explicit multithreading Example systems Motivation Organization NUMA Pros and cons Vector computation   Approaches to vector computation IBM 3090 vector facility

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