Handout #6 6.823 Computer System Architecture Cache Implementations Direct-mapped Cache The following diagram shows how a direct-mapped cache is organized. To read a word from the cache, the input address is set by the processor. Then the index portion of the address is decoded to access the proper row in the tag memory array and in the data memory array. The selected tag is compared to the tag portion of the input address to determine if the access is a hit or not. At the same time, the corresponding cache block is read and the proper line is selected through a MUX. Input Address Tag 2b: cache line size (bytes) Index . Tag Status • • • • • • . . 2b-2 data words Tag Decoder Data Decoder Valid Bit • • • . • • • . . . . . . . . MUX Comparator Valid Output Driver Data Output Driver Figure H6-A: A direct-mapped cache implementation In the tag and data array, each row corresponds to a line in the cache. For example, a row in the tag memory array contains one tag and two status bits (valid and dirty) for the cache line. For direct-mapped caches, a row in the data array holds one cache line. 1 Four-way Set-associative Cache The implementation of a 4-way set-associative cache is shown in the following diagram. (An nway set-associative cache can be implemented in a similar manner.) The index part of the input address is used to find the proper row in the data memory array and the tag memory array. In this case, however, each row (set) corresponds to four cache lines (four ways). A row in the data memory holds four cache lines (for 32-bytes cache lines, 128 bytes), and a row in the tag memory array contains four tags and status bits for those tags (2 bits per cache line). The tag memory and the data memory are accessed in parallel, but the output data driver is enabled only if there is a cache hit. 2b: cache line size (bytes) Input Address Tag Index .. T S T S T S T S • • • • • • • • • • • • • • • • • • • • • • • • = = .. .. 4×2b-2 data words Tag Decoder Data Decoder •••• •••• •••• •••• •••• •••• •••• •••• •••• •••• •••• •••• .. .. .. .. MUX MUX MUX MUX .. Valid Bit = .. = .. Comparator Buffer Driver Valid Output Driver Figure H6-B: A 4-way set-associative cache implementation 2 .. ..

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